This paper describes design optimization and performances of hybrid optical transmission lines consisting of effective-area-enlarged pure silica core fiber and dispersion compensating fiber. As a result of the design optimization, considering low nonlinearity and good bending characteristic, the developed fibers exhibit a span average loss of 0.208 dB/km, a span average dispersion slope of 0.02 ps/nm2/km and low nonlinearity with an equivalent effective area of 60 µm2. Further optimization of the relationship among the nonlinearity, the dispersion slope and the bending characteristic enables perfectly dispersion-flattened hybrid optical transmission lines exhibiting a low transmission loss of 0.211 dB/km, low nonlinearity with an equivalent effective area of 60 µm2 and small dispersion deviation of 0.03 ps/nm/km in a wavelength band wider than 40 nm.

The low bias region of the base current has been studied in SiGe HBTs and shown to arise from tunneling at the emitter periphery. Tunneling also describes the reverse bias base-emitter current, which we believe is enhanced by mid-gap states. The reverse bias causes damage to the base-emitter region, increasing the base current. We also show that after a short period of severe reverse bias stress the base current displays random telegraph signals. These phenomena are often observed in silicon bipolar transistors, confirming that the incorporation of SiGe has not produced any other undesirable characteristics.

Current-voltage characteristics of Cr-doped hydrogenated amorphous silicon-V (Cr/p+a-Si:H/V) analogue memory switching devices have been measured over a wide range of device resistance from several kilo-ohms to several hundred kilo-ohms, and over a temperature range from 13 K to 300 K. Both the bias and temperature dependence of the conductance show similar characteristics to that of metal-insulator heterogeneous materials (i.e. discontinuous or granular metallic films), which are analysed in terms of activated tunnelling mechanism. A modified filamentary structure for the Cr/p+a-Si:H/V switching devices is proposed. The influence of embedded metallic particles on memory switching is analysed and discussed.

Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.

We analyze electron transport of silicon single-electron transistors (Si SETs) with an ultra-small quantum dot using a master-equation model taking into account the discreteness of quantum levels and the finiteness of scattering rates. In the simulated SET characteristics, aperiodic Coulomb blockade oscillations, fine structures and negative differential conductances due to the quantum mechanical effects are superimposed on the usual Coulomb blockade diagram. These features are consistent with the previously measured results. Large peak-to-valley current ratio of negative differential conductances at room temperature is predicted for Si SETs with an ultra-small dot whose size is smaller than 3 nm.

Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p+-n+ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.

High-speed digital data transmission services with mobile equipment are becoming available. Though the visual signal is one of the expected media to be used with such transmission capabilities, the bandwidth of visual signal is much broader than the provided transmission bandwidth in general. Therefore efficient video encoding algorithms have to be introduced. The ITU-T Recommendation H.263 and ISO/IEC MPEG-4 are very powerful encoding algorithms for a wide range of video sequences. But a large amount of bits are generated in highly active scenes to encode them using such conventional methods. This results in frame skipping and degradation of decoded picture quality. In order to keep these degradations as low as possible, we proposed a Dynamic Resolution Conversion (DRC) method of the prediction error. In the method, a reduced resolution encoding is carried out when the input scene is highly active. Simulation results show that the proposed scheme can improve both coding frame rate and picture quality in a highly active scene. We also present in this paper that some analysis for the performance of the DRC method under the error prone environment that is inevitable with mobile communications.

We have proposed parallel optical interconnection technology, or ParaBIT, for high-throughput, low-cost optical interconnections and already developed a prototype parallel optical interconnect module called "ParaBIT-0," which has a total throughput of 28 Gb/s (700 Mb/s 40 channels). We are now developing a compact, high-throughput module called "ParaBIT-1," which has a total throughput of 60 Gb/s (1.25 Gb/s 48 channels) and is designed to achieve the highest-ever throughput density of 3.3 Gb/s/cc. In this paper, we describe the packaging structure, optical coupling structure and transmission characteristics of ParaBIT-1. We also discuss the technical prospect of realizing a parallel optical interconnect module with the bit rate of 2.5 Gb/s/ch.

Based on the partially-depleted, thin-film SOI/CMOS technology, the influence of reduced junction capacitance on the performance of the elementary gates and large scale gate array chip is reviewed. To further reduce the power consumption, SOI-specific device configurations, in which the body-bias is individually controlled, are effective in lowering the supply voltage and hence the power consumption while keeping the circuit speed. Two attempts are introduced: (1) DTMOS (Dynamic-Threshold MOS)/SOI to achieve ultra low-voltage and yet high-speed operation, and (2) ABB (Active-Body-Bias) MOS to enhance the current drive under the low supply voltage.

We have developed a highly integrated liquid-crystal-on-silicon microdisplay for virtual reality applications. The silicon panel of 704 576 pixels was designed and fabricated by a custom 0.35 µm complementary metal oxide semiconductor (CMOS) technology with emphasis on surface planarization. Topographic variation of less than 100 within the pixels was achieved. The pixel pitch was 9.6 µm, fill factor was 88% and display area was 0.36" in diagonal. Eight-bit digital data drivers and gamma-correction circuitry were integrated onto the silicon panel for true gray scale and full color representation. The display panel was assembled with a mixed twisted nematic and birefringence liquid crystal cell for high contract at CMOS compatible voltage. Chromatic characterization of the display using 3-color-in-1 light emitting diode (LED) as light source was performed. Contrast ratios on the pixel array were 95, 72 and 56, respectively, for red, green and blue colors at 3 V root-mean-squared voltage. In addition, a three-dimensional (3D) video stream in interlaced format was generated by a 3D modeling code for test and demonstration. Control logic was implemented to extract the left and right video frames and perform system timing synchronization. The silicon microdisplay was driven in frame inversion and by color sequence. With two sets of silicon microdisplays and eyepieces for each eye, we have demonstrated a 3D stereoscopic display based on the silicon microdisplay technology.

Silicone contamination due to SiO2 caused by decomposition of silicone vapor is recognized as an undesirable phenomenon in electrical contact applications. The effects of silicone vapor adsorbed on the contact surface were examined by using micro relay contacts. The amount of SiO2 formed by the decomposition of silicone vapor is expected to depend on the amount of silicone vapor adsorbed on the contact surface. Hence, first of all, an increase in the thickness of the film from the adsorbed silicone vapor as a function of exposure time was clarified for the static state of the surface. The thickness of the film of adsorbed silicone vapor increased in proportion to exposure time and saturated at a thin monolayer. Moreover, in this exposure period, the thickness was affected by the concentration of the silicone vapor. After the thickness of the molecular layer saturated, the thickness of the layer was not influenced by the concentration of the silicone vapor. Next, from these results obtained by examination of exposure in the static state, the following is deducible. The silicone molecule adsorbs easily on the contact surface during the opening period of making and breaking contacts as well as in the static state. As the time the contacts are open determines the exposure time, the amount of adsorbed silicone molecules depends on the switching rate (operation per second). Contact failure due to increases in contact resistance might be affected by the switching rate in a silicone environment. Accordingly, contact resistance characteristic was examined over a wide range of switching rates. It was found that number of operations up to contact failure was affected markedly by the switching rate. Namely, the number of operations up to contact failure decreases as the switching rate increases. However, once a very thin layer such as the monolayer has formed, the film thickness ceases to grow. Accordingly, after the very thin layer is formed, the occurrence of contact failure does not depend on the concentration of silicone and the switching rate.

Sticking is one of dominant characteristics of reliability in relays for medium current loads from several amperes to several dozen amperes, which are used for relays for automobiles, industrial control units or power supplies of household electrical appliances. Correlations between the release failures due to sticking and contact characteristics such as arc discharges, material parameters and design factors in relays have never been always made clear. This puts difficulty in the way of reasonable development of contact materials and rational design of relays. So, dependence of electrical load conditions on sticking characteristics are investigated, using the Ag-CdO contacts which have had high practical use to relays for medium current loads. Furthermore, relationship among the sticking characteristics, arc discharge characteristics and contact surface properties after operations are studied. Mechanism of sticking is considered on the basis of those data. The results are as follows: (1) Sticking phenomenon occurs intermittently from initial operations and lasts to the end. (2) The µ + 2 σ value (the sum of the mean value and the integral multiple of the standard deviation of sticking force) increases in proportion to the circuit current. On the other hand, it has the maximum value at a circuit voltage, slightly less than the minimum arc voltage. (3) Factors causing the sticking are considered to be divided into direct factors and its root factors. It is considered that a dominant direct factor is welding, and that its root factor is bridge or welding by Joule's heat. On the other hand, the sticking force becomes rather lower as the circuit voltage increases, in the circuit voltage range where regular arc discharge occurs.

A tunable optical Fabry-Perrot filter was designed by setting a single-mode optical fiber normal to the diaphragm of a capacitive pressure sensor. The silicon diaphragm is deflected by the electrostatic force generated by applying a voltage to the capacitive electrodes. According to the movement of the diaphragm, the peak wavelength changed from 1546 to 1551 nm when applied voltage was increased from 20 to 50 V. The relationship of the wavelength change to the applied voltage was derived from the silicon diaphragm deflection theory. That measured change of the wavelength agrees well with the wavelength change calculated from this relationship. The commercial pressure sensors are expected to be able to be used as a tunable optical filter.

In this letter, we remark a well-known nonlinear filtering technique realize immediate effect to suppress the influence of the additive measurement noise in the input to a set theoretic linear blind deconvolution scheme. Numerical examples show ε-separating nonlinear pre-filtering techniques work suitably to this noisy blind deconvolution problem.

This work presents the first comprehensive full-band Monte Carlo model for the simulation of silicon/silicon-germanium devices with arbitrary germanium profiles. The model includes a new CPU and memory efficient method for the discretization of the Brillouin zone based on adaptive nonuniform tetrahedral grids and a very efficient method for transfers through heterointerfaces in the case of irregular -space grids. The feasibility of the FB-MC simulation is demonstrated by application to an industrial HBT with a graded germanium profile and different aspects of the microscopic carrier transport are discussed. Internal distributions of the transistor are calculated with a very low noise level and high efficiency allowing a detailed investigation of the device behavior.

A first-order investigation of the transport and energy-loss processes in silicon dioxide is worked out in the frame of the Spherical-Harmonics solution of the Boltzmann Transport Equation. The SiO2 conduction band is treated as a single-valley spherical and parabolic band. The relevant scattering mechanisms are modeled consistently: both the polar and nonpolar electron-phonon scattering mechanisms are considered. The scattering rates for each contribution are analyzed in comparison with Monte Carlo data. A number of macroscopic transport properties of electrons in SiO2 are worked out in the steady-state regime for a homogeneous bulk structure. The investigation shows a good agreement in comparison with experiments in the low-field regime and for different temperatures.

Silicon self-interstitial atom diffusion and implantation induced damage were studied by using molecular dynamics methods. The diffusion coefficient of interstitial silicon was calculated using molecular dynamics method based on the Stillinger-Weber potential. A comparison was made between the calculation method based on the Einstein relationship and the method based on a hopping analysis. For interstitial silicon diffusion, atomic site exchanges to the lattice atoms occur, and thus the total displacement-based calculation underestimates the ideal value of the diffusivity of the interstitial silicon. In addition with calculating the diffusion constant, we also identified its migration pathway and barrier energy in the case of Stillinger-Weber potential. Through a study of molecular dynamics calculation for the arsenic ion implantation process, it was found that the damage self-recovering process depends on the extent of damage. That is, damage caused by a single large impact easily disappears. In contrast, the damage leaves significant defects when two large impacts in succession cause an overlapped damage region.

This paper reports the implementation in three dimensions (3D) of diffusion models for low dose implanted dopants in silicon and the various numerical issues associated with it. In order to allow the end-users to choose between high accuracy or small calculation time, a conventional and 5-species diffusion models have been implemented in the 3D module DIFOX-3D belonging to the PROMPT plateform. By comparison with one and two-dimensional (1D and 2D) simulations performed with IMPACT-4, where calibrated models exist, the validity of this 3D models have been checked. Finally, the results obtained for a 3-dimensional simulation of a rapid thermal annealing step involved in the manufacturing of a MOS transistor are presented what show the capability of this module to handle the optimization of real devices.

Micropatterning of organosilane self-assembled monolayers (SAMs) was demonstrated on the basis of photolithography using an excimer lamp radiating vacuum ultra-violet (VUV) light of 172 nm in wavelength. This lithography is generally applicable to micropatterning of organic thin films including alkyl and fluoroalkyl SAMs, since its patterning mechanism involves cleavage of C-C bonds in organic molecules and subsequent decomposition of the molecules. In this study, SAMs were prepared on Si substrates covered with native oxide by chemical vapor deposition in which an alkylsilane, that is, octadecyltrimethoxysilane [CH3(CH2)17Si(OCH3)3, ODS] or a fluoroalkylsilane, that is, 1H, 1H, 2H, 2H-perfluorodecyltrimethoxy-silane [CF3(CF2)7CH2CH2Si(OCH3)3, FAS] were used as precursors. Each of these SAMs was photoirradiated through a photomask placed on its surface. As confirmed by atomic force microscopy and x-ray photoelectron spectroscopy, the SAMs were decomposed and removed in the photoirradiated area while the masked areas remained undecomposed. A micropattern of 2 µm in width was successfully fabricated. Furthermore, microstructures composed of two different SAMs, that is, ODS and FAS, were fabricated as follows. For example, an ODS-SAM was first micropatterned by the VUV-lithography. Since, the VUV-exposed region on the ODS-SAM showed an affinity to the chemisorption of organosilane molecules, the second SAM, i. e. , FAS, confined to the photolithographically defined pattern was successfully fabricated. Due to the electron negativity of F atoms, the FAS covered region showed a more negative surface potential than that of the ODS surface: its potential difference was ca. 120 mV as observed by Kelvin probe force microscopy.

We have reviewed recent progress on arrayed waveguide gratings for DWDM applications. AWGs can be used to realize not only mux/demux filters with various channel spacings, but also highly integrated optical components.