A parallel multiplexing scheduling (PMS) scheme is proposed for distributed antenna systems (DAS), which greatly improves average system throughput due to multi-user diversity and multi-user multiplexing. However, PMS has poor fairness because of the use of the "best channel selection" criteria in the scheduler. Thus we present a parallel proportional fair scheduling (PPFS) scheme, which combines PMS with proportional fair scheduling (PFS) to achieve a tradeoff between average throughput and fairness. In PPFS, the "relative signal to noise ratio (SNR)" is employed as a metric to select the user instead of the "relative throughput" in the original PFS. And only partial channel state information (CSI) is fed back to the base station (BS) in PPFS. Moreover, there are multiple users selected to transmit simultaneously at each slot in PPFS, while only one user occupies all channel resources at each slot in PFS. Consequently, PPFS improves fairness performance of PMS greatly with a relatively small loss of average throughput compared to PFS.

The All-Pairs Shortest Paths (APSP) problem is a graph problem which can be solved by a three-nested loop program. The Cell Broadband Engine (Cell/B.E.) is a heterogeneous multi-core processor that offers the high single precision floating-point performance. In this paper, a solution of the APSP problem on the Cell/B.E. is presented. To maximize the performance of the Cell/B.E., a blocked algorithm for the APSP problem is used. The blocked algorithm enables reuse of data in registers and utilizes the memory hierarchy. We also describe several optimization techniques for effective implementation of the APSP problem on the Cell/B.E. The Cell/B.E. achieves the performance of 8.45 Gflop/s for the APSP problem by using one SPE and 50.6 Gflop/s by using six SPEs.

We propose a dimension reduction algorithm for the receiver of the downlink of direct-sequence code-division multiple access (DS-CDMA) systems in which both the transmitters and the receivers employ antenna arrays of multiple elements. To estimate the high order channel parameters, we develop a layered architecture using dimension-reduced parameter estimation algorithms to estimate the frequency-selective multipath channels. In the proposed architecture, to exploit the space-time geometric characteristics of multipath channels, spatial beamformers and constrained (or unconstrained) temporal filters are adopted for clustered-multipath grouping and path isolation. In conjunction with the multiple access interference (MAI) suppression techniques, the proposed architecture jointly estimates the direction of arrivals, propagation delays, and fading amplitudes of the downlink fading multipaths. With the outputs of the proposed architecture, the signals of interest can then be naturally detected by using path-wise maximum ratio combining. Compared to the traditional techniques, such as the Joint-Angle-and-Delay-Estimation (JADE) algorithm for DOA-delay joint estimation and the space-time minimum mean square error (ST-MMSE) algorithm for signal detection, computer simulations show that the proposed algorithm substantially mitigate the computational complexity at the expense of only slight performance degradation.

The inflection S-shaped software reliability growth model (SRGM) proposed by Ohba (1984) is one of the well- known SRGMs. This paper deals with the optimal software release problem with regard to the expected software cost under this model based on the Bayesian approach. To reflect the effect of the learning experience for the updated software system, we consider several improvement factors to adjust the values of parameters characterizing the inflection S-shaped SRGM. Appropriate prior distributions are assumed for such factors and the expected total software cost is formulated. The optimal release time is shown to be finite and uniquely determined. Because of the flexibility of prior distributions, the proposed Bayesian methods may be applied in many different situations. Numerical results are presented on the basis of the real data.

An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the effective data capacity, and for an optimal exploitation of this capacity for given power dissipation. At high level, this asks for a new view on the so-called client-server relations in the chain. To substantiate this vision, some examples of research projects in our group are addressed. These include FE-driven transmission schemes, duty-cycled operation with wake-up radio, programmable FEs, smart antenna-FE combinations, smart and flexible converters, and smart pre and post correction.

In this paper the time-domain analysis of two parallel traces is investigated. First, the telegrapher's equations for transmission line are applied to the parallel traces on printed circuit board (PCB), and are solved by using the mode decomposition technique. The time-domain solutions are then obtained by using the inverse Laplace transform. Although the Fourier-transform technique is also applicable for this problem, the solution is given numerically. Contrarily, the inverse Laplace transform successfully leads to an analytical expression for the transmission characteristics. The analytical expression is represented by series, which clearly explains the coupling mechanism. The analytical expression for the fundamental section of a meander delay line is investigated in detail. The analytical solution is validated by measurements, and the characteristics of the distortions in the output waveforms of meander delay lines due to the crosstalk are also investigated.

We propose an automatic generative method for stylus style CG as automatic generative method for non-photorealistic CG.

This letter focuses on the simplified capacity evaluation for the downlink of a distributed antenna system (DAS) with random antenna layout. Based on system scale-up, we derive a good approximation of the downlink capacity by developing the results from random matrix theory. We also propose an iterative method to calculate the unknown parameters in the approximated expression of the downlink capacity. The approximation is illustrated to be quite accurate and the iterative method is shown to be quite efficient by Monte Carlo simulations.

Distributed video coding (DVC) technology has been considered to be capable of reducing the processing complexity of the encoder immensely, while majority of the computational overheads are taken over by the decoder. In the common DVC framework, the pictures are decoded using the Wyner-Ziv encoded bit stream received from the encoder and the side information estimated using previously decoded information. As a result, accuracy of the side information estimation is very critical in improving the coding efficiency. In this paper we propose a novel side information refinement technique for DVC using multiple side information streams and sequential motion compensation with luminance and chrominance information involving iterative fusion of parallel information streams. In the bit plane wise coding architecture, previously decoded higher order bit planes are incrementally used to perform the motion estimation jointly in luminance and chrominance spaces to estimate multiple redundant bit streams for iterative fusion to produce more improved side information for subsequent bit planes. Simulation results show significant objective quality gain can be achieved at the same bit rate by utilizing the proposed refinement algorithms.

ε-filter is a nonlinear filter for reducing noise and is applicable not only to speech signals but also to image signals. The filter design is simple and it can effectively reduce noise with an adequate filter parameter. This paper presents a method for estimating the optimal filter parameter of ε-filter based on signal-noise decorrelation and shows that it yields the optimal filter parameter concerning a wide range of noise levels. The proposed method is applicable where the noise to be removed is uncorrelated with signal, and it does not require any other knowledge such as noise variance and training data.

In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loops, however, there is still much room to improve the performance by exploiting the parallelism. In this paper, we, for the first time, propose a method to utilize pipelining techniques and take interconnect delays into account together so as to improve the quality of high level synthesis. The proposed method has the following two characteristics: 1) it separates the consideration of interconnect delay from computation delay, and allows concurrent data transfer and computation; 2) it belongs to modulo scheduling framework, in the sense that all iterations have identical schedules, and are initiated periodically. We evaluate our method from two different points of view. Firstly, we compare our method with an existing interconnect-aware high level synthesis that does not utilize pipelining techniques, and the experimental results show that our method can obtain about 3.4 times performance improvement on average. Secondly, we compare our method with an existing pipeline synthesis that does not consider interconnect delays, and the results show that our method can obtain about 1.5 times performance improvement on average. In addition, we also evaluate our proposed architecture and the experimental results demonstrate that it is better than existing architecture in [1].

Recently, Au et al. proposed a practical hierarchical identity-based encryption (HIBE) scheme and a hierarchical identity-based signature (HIBS) scheme. In this paper, we point out that there exists security weakness both for their HIBE and HIBS scheme. Furthermore, based on q-ABDHE, we present a new HIBE scheme which is proved secure in the standard model and it is also efficient. Compared with all previous HIBE schemes, ciphertext size as well as decryption cost are independent of the hierarchy depth. Ciphertexts in our HIBE scheme are always just four group elements and decryption requires only two bilinear map computations.

This paper presents two power-saving designs for Quadratic Polynomial Permutation (QPP) interleave address generator of which interleave length K is fixed and unfixed, respectively. These designs are based on our observation that the quadratic term f2x2%K of f(x) = (f1x+f2x2)%K, which is the QPP address generating function, has a short period and is symmetric within the period. Power consumption is reduced by 27.4% in the design with fixed-K and 5.4% in the design with unfixed-K on the average for various values of K, when compared with existing designs.

Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.

We propose two vertical handoff schemes for cellular network and wireless local area network (WLAN) integration: integrated service-based handoff (ISH) and integrated service-based handoff with queue capabilities (ISHQ). Compared with existing handoff schemes in integrated cellular/WLAN networks, the proposed schemes consider a more comprehensive set of system characteristics such as different features of voice and data services, dynamic information about the admitted calls, user mobility and vertical handoffs in two directions. The code division multiple access (CDMA) cellular network and IEEE 802.11e WLAN are taken into account in the proposed schemes. We model the integrated networks by using multi-dimensional Markov chains and the major performance measures are derived for voice and data services. The important system parameters such as thresholds to prioritize handoff voice calls and queue sizes are optimized. Numerical results demonstrate that the proposed ISHQ scheme can maximize the utilization of overall bandwidth resources with the best quality of service (QoS) provisioning for voice and data services.

Two adaptive energy detectors are proposed for cognitive radio systems to detect the primary users. Unlike the conventional energy detector (CED) where a decision is made after receiving all samples, our detectors make a decision with the sequential arrival of samples. Hence, the sample size of the proposed detectors is adaptive. Simulation results show that for a desired performance, the average sample size of the proposed detectors is much less than that of the CED. Therefore, they are more agile than the CED.

We address the problem of multiuser co-channel interference scheduling in multicell interference-limited networks. Our target is to optimize the network capacity under the SIR-balanced power control policy. Since it's difficult to optimize the original problem, we derive a new problem which maximizes the lower bound of the network capacity. Based on the analysis of this new problem, we propose an interference matched scheduling algorithm. This algorithm considers the caused co-channel interference and the channel conditions to schedule the "matched" users at the same time. We prove that this interference matched scheduling algorithm optimizes the lower bound of the network capacity for any arbitrary numbers of cells and users. Moreover, this scheduling method is low-complexity and can be implemented in a fully distributed fashion. Simulation results reveal that the performance of the proposed algorithm achieves near optimal capacity, even though it does not optimize the network capacity directly. Finally, the proposed algorithm holds a great gain over formerly proposed round robin and power matched scheduling method, especially when the scale of the network is large.

A method that jointly estimates the carrier frequency offset (CFO), channel and symbol timing for orthogonal frequency division multiplexing (OFDM) is proposed in this letter. Based on the characteristic of cyclic training symbols in the frequency domain, the joint estimation is divided into three separate estimations. The CFO and equivalent channel impulse response (CIR) are first estimated by an iterative joint maximum likelihood estimation (JMLE), then the symbol timing offset (STO) is obtained by the assistance of equivalent CIR, finally the CIR is calculated based on the equivalent CIR after known STO and CFO. In our proposed method, the effect of imperfect CIR is considered in the CFO estimator. Moveover, a procedure, which eliminates the inverse operation of a covariance matrix at each iterative process, was adopted to reduce the complexity of our proposed method. Simulations show that the proposed method is capable of retaining the same bit error rate as joint CFO and CIR maximum likelihood estimation without symbol timing error.

To mitigate the asynchronous ICI (Inter-Cell Interference), SCM (Spatial Covariance Matrix) of the asynchronous ICI plus background noise should be accurately estimated for MIMO-OFDMA (Multiple-input Multiple-output-Orthogonal Frequency Division Multiple Access) system. Generally, it is assumed that the SCM of the asynchronous ICI plus background noise is estimated by using training symbols. However, it is difficult to measure the interference statistics for a long time and considering that training symbols are not appropriate for OFDMA system such as LTE (3GPP Long Term Evolution). Therefore, noise reduction method is required to improve the estimation accuracy. Although the conventional time-domain low-pass type weighting method can be effective for noise reduction, it causes significant estimation error due to the spectral leakage in practical OFDM system. Therefore, we propose a time-domain sinc type weighing method which can not only reduce noise effectively minimizing estimation error caused by the spectral leakage but also can be implemented using frequency-domain weighted moving average filter easily. We also consider the iterative CFR (Channel Frequency Response) and SCM estimation method which can effectively reduce the estimation error of both CFR and SCM, and improve the performance for LTE system. By using computer simulation, we show that the proposed method can provide up to 2.5 dB SIR (Signal to Interference Ratio) gain compared with the conventional method, and verify that the proposed method is attractive and suitable for implementation with stable operation.