In this paper, we study the capacity and performance of nonorthogonal pulse position modulation (NPPM) for Ultra-Wideband (UWB) communication systems over both AWGN and IEEE802.15.3a channels. The channel capacity of NPPM is determined for a time-hopping multiple access UWB communication system. The error probability and performance bounds are derived for a multiuser environment. It is shown that with proper selection of the pulse waveform and modulation index, NPPM can achieve a higher capacity than orthogonal PPM, and also provide better performance than orthogonal PPM with the same throughput.

This paper presents a system architecture for sensor signal digitization utilizing a band-pass sigma-delta modulator (BP ΣΔM). The first version of the proposed system architecture was implemented in 5 V 0.7 µm CMOS technology. The proposed system architecture is useful for our capacitive pressure sensor measurement. The paper describes the possibilities of using the proposed enhanced system architecture in impedance spectroscopy and in capacitive pressure sensor measurement. The BP ΣΔM is well suited for wireless applications. This paper shows another way how to use its advantages.

ε-filter is a nonlinear filter for reducing noise and is applicable not only to speech signals but also to image signals. The filter design is simple and it can effectively reduce noise with an adequate filter parameter. This paper presents a method for estimating the optimal filter parameter of ε-filter based on signal-noise decorrelation and shows that it yields the optimal filter parameter concerning a wide range of noise levels. The proposed method is applicable where the noise to be removed is uncorrelated with signal, and it does not require any other knowledge such as noise variance and training data.

This paper presents two power-saving designs for Quadratic Polynomial Permutation (QPP) interleave address generator of which interleave length K is fixed and unfixed, respectively. These designs are based on our observation that the quadratic term f2x2%K of f(x) = (f1x+f2x2)%K, which is the QPP address generating function, has a short period and is symmetric within the period. Power consumption is reduced by 27.4% in the design with fixed-K and 5.4% in the design with unfixed-K on the average for various values of K, when compared with existing designs.

The key issue in cognitive radio is to design a reliable spectrum sensing method that is able to detect the signal in the target channel as well as to recognize its type. In this paper, focusing on classifying different orthogonal frequency-division multiplexing (OFDM) signals, we propose a two-step detection and identification approach based on the analysis of the cyclic autocorrelation function. The key parameters to separate different OFDM signals are the subcarrier spacing and symbol duration. A symmetric peak detection method is adopted in the first step, while a pulse detection method is used to determine the symbol duration. Simulations validate the proposed method.

A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

Recently, Au et al. proposed a practical hierarchical identity-based encryption (HIBE) scheme and a hierarchical identity-based signature (HIBS) scheme. In this paper, we point out that there exists security weakness both for their HIBE and HIBS scheme. Furthermore, based on q-ABDHE, we present a new HIBE scheme which is proved secure in the standard model and it is also efficient. Compared with all previous HIBE schemes, ciphertext size as well as decryption cost are independent of the hierarchy depth. Ciphertexts in our HIBE scheme are always just four group elements and decryption requires only two bilinear map computations.

In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loops, however, there is still much room to improve the performance by exploiting the parallelism. In this paper, we, for the first time, propose a method to utilize pipelining techniques and take interconnect delays into account together so as to improve the quality of high level synthesis. The proposed method has the following two characteristics: 1) it separates the consideration of interconnect delay from computation delay, and allows concurrent data transfer and computation; 2) it belongs to modulo scheduling framework, in the sense that all iterations have identical schedules, and are initiated periodically. We evaluate our method from two different points of view. Firstly, we compare our method with an existing interconnect-aware high level synthesis that does not utilize pipelining techniques, and the experimental results show that our method can obtain about 3.4 times performance improvement on average. Secondly, we compare our method with an existing pipeline synthesis that does not consider interconnect delays, and the results show that our method can obtain about 1.5 times performance improvement on average. In addition, we also evaluate our proposed architecture and the experimental results demonstrate that it is better than existing architecture in [1].

Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.

Distributed video coding (DVC) technology has been considered to be capable of reducing the processing complexity of the encoder immensely, while majority of the computational overheads are taken over by the decoder. In the common DVC framework, the pictures are decoded using the Wyner-Ziv encoded bit stream received from the encoder and the side information estimated using previously decoded information. As a result, accuracy of the side information estimation is very critical in improving the coding efficiency. In this paper we propose a novel side information refinement technique for DVC using multiple side information streams and sequential motion compensation with luminance and chrominance information involving iterative fusion of parallel information streams. In the bit plane wise coding architecture, previously decoded higher order bit planes are incrementally used to perform the motion estimation jointly in luminance and chrominance spaces to estimate multiple redundant bit streams for iterative fusion to produce more improved side information for subsequent bit planes. Simulation results show significant objective quality gain can be achieved at the same bit rate by utilizing the proposed refinement algorithms.

Time-interleaving is an efficient approach to increase the effective sampling rate of the ΣΔ modulators, but time-interleaved (TI) ΣΔ modulators are sensitive to channel mismatch, which causes the quantization noise folded back into the band of interest. To reduce the folded noise caused by the channel mismatch of two-channel TI ΣΔ modulators, a low-power second-order two-channel TI ΣΔ modulator is proposed. The noise transfer function (NTF) of the modulator is a band-pass filter. By using this band-pass NTF, the folded noised can be reduced. The entire modulator can be implemented by employing three op-amps, which is beneficial for power consumption. The circuit of implementation for the proposed modulator is designed in 0.18 µm COMS technology. The proposed modulator can achieve a SNDR of 78.9 dB with a channel mismatch of 0.5% and a linear gradient mismatch of 0.4% for unity sampling capacitors. Monte Carlo simulation is done with a random Gaussian mismatch of 0.4% standard deviation for all capacitors, resulting in an average SNDR of 80.5 dB. It is indicated that the proposed TI modulator is insensitive to the channel mismatch. The total power consumption is 19.5 mW from a 1.8 V supply.

This letter focuses on the simplified capacity evaluation for the downlink of a distributed antenna system (DAS) with random antenna layout. Based on system scale-up, we derive a good approximation of the downlink capacity by developing the results from random matrix theory. We also propose an iterative method to calculate the unknown parameters in the approximated expression of the downlink capacity. The approximation is illustrated to be quite accurate and the iterative method is shown to be quite efficient by Monte Carlo simulations.

An analytical method for estimating coupling between microstrip lines in arbitrary directions on adjacent layers in multi-layer printed circuit boards is studied: one line is embedded and the other is on the surface layer. Coupling or crosstalk has been estimated by development of a circuit-concept approach based on modified telegrapher's equations of the Agrawal approach instead of the Taylor approach for some computational advantages. Electromagnetic fields from the embedded microstrip line and the microstrip line on the surface can be obtained by using the electric image method for dielectric substrates. To verify the proposed approach, we conducted some experiments and compared the results of our approach with those of measurement and a commercial electromagnetic solver.

In this letter, we consider a problem of global stabilization of a class of approximately feedback linearized systems. We propose a new nonlinear control approach which includes a nonlinear controller and a Lyapunov-based design method. Our new nonlinear control approach broadens the class of systems under consideration over the existing results.

This paper proposes a frequency domain nulling filter and Turbo equalizer to suppress interference in the uplink of one-cell reuse single-carrier time division multiple access (TDMA) systems. In the proposed system, the desired signal in a reference cell is interfered by interference signals including adjacent-channel interference (ACI), co-channel interference (CCI), and intersymbol interference (ISI). At the transmitter, after a certain amount of spectrum is nulled considering the expected CCI, the suppressed power due to nulling is reallocated to the remaining spectrum components so as to keep the total transmit power constant. In this process, when mitigation of ACI is necessary, after a certain amount of spectrum at both edges is nulled using an edge-removal filter, the aforementioned process is conducted. At the receiver, frequency domain SC/MMSE Turbo equalizer (FDTE) is employed to suppress ISI due to spectrum nulling process in the transmitter as well as the multipath fading. Computer simulations confirm that the proposed scheme is effective in suppression of CCI, ACI and ISI in one-cell reuse single-carrier TDMA systems.

A decoupling device that can be used for millimeter-waves is required to reduce the effect of the parasitic impedance at the grounded terminal of the power supply. The frequently used decoupling capacitor is not appropriate because it has self-resonance characteristics due to the parasitic inductance. To realize resonance-free wideband decoupling, a high-attenuation power line (HAPL) is proposed. The HAPL has constant input impedance equal to its characteristic impedance, and has constant isolation unaffected by the phase constant and the terminal impedance. Furthermore, the HAPL contributes to the area reduction of the millimeter-wave circuits because it simultaneously acts as a power line and a decoupling device. The HAPL was fabricated with a 90 nm CMOS process. The proposed structure increases parallel conductance and capacitance using an MOS capacitor and its equivalent series resistance, therefore realizing high attenuation and resonance suppression while reducing characteristic impedance. With a 200-µm-long HAPL, Re (S11) was less than -0.9 and isolation was more than 25 dB, from 50 GHz to 90 GHz including unlicensed bands used for wireless personal area network and radar application. As a result, power-supply network with wideband decoupling is realized by simply connecting power-supply pads and feeding point via the HAPL. The HAPL is expected to contribute to the simple and compact design of millimeter-wave circuits.

We propose two vertical handoff schemes for cellular network and wireless local area network (WLAN) integration: integrated service-based handoff (ISH) and integrated service-based handoff with queue capabilities (ISHQ). Compared with existing handoff schemes in integrated cellular/WLAN networks, the proposed schemes consider a more comprehensive set of system characteristics such as different features of voice and data services, dynamic information about the admitted calls, user mobility and vertical handoffs in two directions. The code division multiple access (CDMA) cellular network and IEEE 802.11e WLAN are taken into account in the proposed schemes. We model the integrated networks by using multi-dimensional Markov chains and the major performance measures are derived for voice and data services. The important system parameters such as thresholds to prioritize handoff voice calls and queue sizes are optimized. Numerical results demonstrate that the proposed ISHQ scheme can maximize the utilization of overall bandwidth resources with the best quality of service (QoS) provisioning for voice and data services.

Two adaptive energy detectors are proposed for cognitive radio systems to detect the primary users. Unlike the conventional energy detector (CED) where a decision is made after receiving all samples, our detectors make a decision with the sequential arrival of samples. Hence, the sample size of the proposed detectors is adaptive. Simulation results show that for a desired performance, the average sample size of the proposed detectors is much less than that of the CED. Therefore, they are more agile than the CED.

A guard trace placed near a signal line reduces common-mode radiation from a printed circuit board. The reduction effect is evaluated by the imbalance difference model, which was proposed by the authors, when the guard trace has exactly the same potential as the return plane. However, depending on interval of ground connection of the guard trace, the radiation can increase when the guard trace resonates. In this paper, the authors show that the increase of radiation is caused by the common mode, and extend the imbalance difference model to explain a mechanism of increase of common-mode radiation. Additionally, the effective via location of the guard trace is proposed to reduce the number of vias. The guard trace voltage due to the resonance excites the common mode at the interface where the cross-sectional structure of the transmission line changes since the common-mode excitation is expressed by the product of the voltage and the difference of current division factors. To suppress the common-mode excitation, the guard trace should be grounded at the point where the cross-sectional structure changes. As a result, the common-mode radiation decreases even when the guard trace resonates.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.