In order to lead an ongoing software project to success, it is important to flexibly control its dynamically-changing software process. However, it is generally impossible not only to exactly pre-define the production process but also to prescribe the process change process (meta-process). To solve the problem, we have focused on communication between the project staff through which process change requests presented by individuals can be immediately shared, designed, verified, validated and implemented. This paper proposes a communication model which can represent a wide variety of communication states between the project manager and developers discussing how to implement process change requests. The communication model has been derived by investigating the sort of process change requests and, based on the model, we have implemented a cooperative process planning system (called CooPs). CooPs is a communication environment designed for software projects and supports information sharing for discussing the process change requests. By using CooPs, the software project can flexibly deal with not only expected change requests but also unexpected ones. To evaluate the applicability of the communication model and the capabilities of CooPs, we have conducted an experiment which is an application of CooPs to the ISPW6 example problem. This paper describes the concepts of CooPs, the system implementation, and the experiment.

In multi-media systems, the type of interactive communication channels is found almost everywhere and plays an important role, as well as the type of unilateral communication channels. In this report, we shall construct a fluctuation theory based on the concept of set-valued mappings, suitable for evaluation, control and operation of interactive communication channels in multi-media systems, complicated and diversified on large scales. Fundamental conditions for availability of such channels are clarified in a form of fixed point theorem for system of set-valued mappings.

This paper develops an algorithm based on the Modular Approach to solve singly constrained separable discrete optimization problems (Nonlinear Knapsack Problems). The Modular Approach uses fathoming and integration techniques repeatedly. The fathoming reduces the decision space of variables. The integration reduces the number of variables in the problem by combining several variables into one variable. Computational experiments for "hard" test problems with up to 1000 variables are provided. Each variable has up to 1000 integer values.

This paper proposes a novel universal line termination scheme for the ONUs (optical network units) of fiber-optic local access systems. Its main feature is that only low cost AD/DA converters for Hi-Fi audio are needed. Because audio AD/DA converters are insufficient for ISDN basic rate access (● 320kbaud) and cause waveform distortion, we develop a simple detection algorithm that does not use any equalizing filter. The algorithm can handle plural channels with one general purpose MPU (micro-processing unit). Based on this, a novel architecture for a fiber-optic local access system is presented that removes the MPUs from each optical network unit (ONU) and places them in the central office (CO). The proposed system yields a small, service-uniform ONU that supports a wide range of narrow-band services (POTS & ISDN) with no distinction. To realize this system at the lowest possible cost, a high-speed code division multiplexing (CDM) scheme with novel code word sets is developed.

For the reduction of the jitter originated from the cell losses in ATM network when CBR traffic is transferred on AAL5, we propose that the receiver maintain a timer whose expiration time is proportional to the cell time of the source traffic plus the standard deviation of the 1-point CDV of the received ATM cells. Moreover, to enhance the granularity of the error or loss detection mechanism in the AAL5 PDUs, we also modified the AAL5 PDU trailer fields so that each cell comprising the AAL5 PDU has a sequence number field. The simulation results show that the peak-to-peak PDV of the AAL5 PDU by the proposed method is less than 69.4% to that by AAL5. Moreover, the AAL5 user receives the same or more error-free transport packets in the proposed algorithm than those in the ITU-T AAL5 for the same network simulation environment.

A partial buffer sharing scheme is proposed as loss-priority control for a finite buffer with batch Poisson inputs under a whole batch acceptance rule. Customer and batch loss probabilities for high- and low-priority customers are derived under this batch acceptance rule using a supplementary variable method. A comparison of the partial buffer sharing scheme and a system without loss-priority control is made in terms of admissible offered load. Whole batch acceptance and partial batch acceptance rules are also compared in terms of admissible offered load.

A typical user is concerned only with the quality of service of a network on an end-to-end basis. Therefore, how end-to-end requirements are mapped into the local switching node requirements and maximum network utilization is a function of network internal design. In this paper, we address the problem of QOS allocation. We derived an optimal QOS allocation policy and decided the maximum utilization bound in a deterministic traffic model. We adopted the worst case delay bound as the end-to-end and local QOS requirement. With (σ, ρ) traffic model, we derived a formula for delay bound and the number of connections. We found that with the delay bound as the QOS metric, there is a significant difference in the performance of allocation policies. We also developed an evaluation strategy to analyze allocation policies. The numerical results for two simple network topologies: tandem network model and uneven traffic load model, compare the equal allocation policy with the optimal allocation policy and show the correctness and efficiency of QOS allocation policy.

A novel multiple-access optical network architecture is presented that not only employs the WDM technique but also divides networks. The subnetworks are connected to each other via a wavelength-dependent interconnection network, and pairs of subnetworks are optically linked with different combinations for each wavelength. Through an analysis of the throughput and delay for the slotted ALOHA protocol, the architecture is confirmed to be improved from the conventional one that employs only the WDM technique. For example, the improvement ratio of the throughput for a four-wavelength network is 2.4, and that for an eight-wavelength network is 4.4.

The aim of this contribution is to take a further step in the study of the impact of chaos-based techniques on classical DS-CDMA systems. The problem addressed here is the sequence phase acquisition and tracking which is needed to synchronize the spreading and despreading sequences of each link. An acquisition mechanism is considered and analyzed in depth to identify analytical expressions of suitable system performance parameters, namely outage probability, link startup delay and expected time to service. Special chaotic maps are considered to show that the choice of spreading sequences can be optimized to accelerate and improve the spreading codes acquisition phase.

Feature selection is an integral part of any pattern recognition system. Removal of redundant features improves the efficiency of a classifier as well as cut down the cost of future feature extraction. Recently neural network classifiers have become extremely popular compared to their counterparts from statistical theory. Some works on the use of artificial neural network as a feature selector have already been reported. In this work a simple feature selection algorithm has been proposed in which a fractal neural network, a modified version of multilayer perceptron, has been used as a feature selector. Experiments have been done with IRIS and SONAR data set by simulation. Results suggest that the algorithm with the fractal network architecture works well for removal of redundant informations as tested by classification rate. The fractal neural network takes lesser training time than the conventional multilayer perceptron for its lower connectivity while its performance is comparable to the multilayer perceptron. The ease of hardware implementation is also an attractive point in designing feature selector with fractal neural network.

We consider a circuit composed of linear capacitors, nonlinear resistors, and dc voltage sources and show the possibility that the total energy dissipated at resistors in the above circuit is smaller than the energy stored at capacitors. Linear passive circuits cannot possess such a property.

This paper proposes non-volatile analog memory circuits using pulse-width modulation (PWM) methods. The conventional analog memory using floating gate device has a trade-off between programming speed and precision because of the constant width of write pulses. The proposed circuits attain high programming speed with high precision by using PWM write pulses. Three circuits are proposed and their performance is evaluated using SPICE simulation. The simulation results show that fast programming time less than 20 µs, high updating resolution of 11 bits, and high precision more than 7 bits are achieved.

It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1 r n). We show that only (r+n/r) tests are required to detect the single stuck-at faults by adding r extra variables to the network.

This paper gives a detailed presentation of a "vision chip" for a very fast detection of motion vectors. The chip's design consists of a parallel pixel array and column parallel block-matching processors. Each pixel of the pixel array contains a photo detector, an edge detector and 4 bits of memory. In the detection of motion vectors, first, the gray level image is binarized by the edge detector and subsequently the binary edge data is used in the block matching processor. The block-matching takes place locally in pixel and globally in column. The chip can create a dense field of motion where a vector is assigned to each pixel by overlapping 2 2 target blocks. A prototype with 16 16 pixels and four block-matching processors has been designed and implemented. Preliminary results obtained by the prototype are shown.

This paper proposes applications of a code-division multiplexing technique to VLSI systems free from interconnection problems. We employ a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier to achieve efficient data transmission. Using orthogonal property of m-sequences, we can multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission with reduced interconnection. Also, randomness of m-sequences offers the high tolerance to interference (jamming), and suppression of dynamic range of signals while maintaining a sufficient signal-to-noise ratio (SNR). We demonstrate application examples of multiplex computing circuits, neural networks, and spread-spectrum image processing to show the advantages.

Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.

This paper presents a new number representation called the Signed-Weight (SW) number system, which is useful for designing configurable counter-tree architectures for digital signal processing applications. The SW number system allows the unified manipulation of positive and negative numbers in arithmetic circuits by adjusting the signs assigned to individual digit positions. This makes possible the construction of highly regular arithmetic circuits without introducing irregular arithmetic operations, such as negation and sign extension in the two's complement representation. This paper also presents the design of a Field-Programmable Digital Filter (FPDF) architecture--a special-purpose FPGA architecture for high-speed FIR filtering--using the proposed SW arithmetic system.

High-speed collision detection is important to realize a highly-safe intelligent vehicle. In collision detection, high-computational power is required to perform matching operation between discrete points on surfaces of a vehicle and obstacles in real-world environment. To achieve the highest performance, a hierarchical matching scheme is proposed based on two representations: the coarse representation and the fine representation. A vehicle is represented as a set of rectangular solids in the fine representation (fine rectangular solids), and the coarse representation, which is also a set of rectangular solids, is produced by enlarging the fine representation. If collision occurs between an obstacle discrete point and a rectangular solid in the coarse representation (coarse rectangular solid), then it is sufficient to check the only fine rectangular solids contained in the coarse one. Consequently, checks for the other fine rectangular solids can be omitted. To perform the hierarchical matching operation in parallel, a hierarchically-content-addressable memory (HCAM) is proposed. Since there is no need to perform matching operation in parallel with fine rectangular solids contained in different coarse ones, the fine ones are mapped onto a matching unit. As a result, the number of matching units can be reduced without decreasing the performance. Under the condition of the same execution time, the area of the HCAM is reduced to 46.4% in comparison with that of the conventional CAM in which the hierarchical matching scheme is not used.

A new hardware algorithm for the block matching video motion estimation is presented. The algorithm works in the full-search fashion but unlike the Full-Search Block Matching Algorithm (FSBMA) it adjusts the number of computations dynamically to variable picture contents. Due to incorporated mechanism of data-driven thresholding, the proposed algorithm performs as four times as less operations comparing to the FSBMA while maintaining the same quality of results. Its hardware implementation is simple and compact. A supportive hardware design as well as simulation results on benchmarks are outlined.

This paper presents a low-power video A/D conversion technique using features of moving pictures. Neighboring frames in typical video sequences and neighboring pixels in each video frame are highly correlated. This property is effectively used for the video A/D conversion to reduce the number of comparators and the resulting power consumption. A set of reference voltages is given to a comparator array so that the iterative A/D conversion converges in the logarithmic order of the prediction error. Simulation results using standard moving pictures showed that the average number of iterations for the A/D conversion is less than 3 for all the moving pictures tested. In the proposed 12 b A/D converter, the number of comparators can be reduced to about 1/5 compared with that of the two-step flash A/D converters, which are commonly used for video applications. The A/D converter is particularly useful for the integration to CMOS image sensors.