In this paper there suggested is a bifurcated (or multiple) input-queued ATM switch in which a buffer for each input port is divided into multiple (m) buffer blocks, i. e. , bifurcated buffers, for enhancement of the limited throughput of the ordinary input-queued switch using a single FIFO. As the contention/arbitration rule for the bifurcated input-queued switching scheme, free and restricted contention rules are come up with and discussed. The free rule allows an input port to switch up to m cells at the cost of internal speedup. With the restricted rule, on the other hand, an input port can switch no more than one cell in a time slot so that the switch operates at the same speed as the external link speed. The throughput bound for the bifurcated input-queued switch is analyzed for both rules through the generalization of the analysis by Karol et al. The throughput bound approaches to 1.0 as m becomes large enough, irrespective of the contention/arbitration rule.

In universal personal telecommunication (UPT) environments, UPT networks retain information related to incall/outcall registration in UPT user service profiles in order to provide incoming UPT calls for UPT users in any location who have registered at a terminal. As UPT networks support incall registration, terminal users can be different from terminal owners, and several UPT users can register for incoming calls on a single terminal. Therefore, appropriate third-party protection procedures are needed to protect the rights of terminal owners. A terminal profile database can be used to store information regarding terminal states and incall UPT users registered on a terminal in order to enable third-party protection procedures. In order to manage information within both the terminal profile and the service profile, we propose a request-based scheme for incall registration/deregistration of UPT users and incall registration resets of terminal owners. We evaluate the performance of the scheme in terms of; 1) total cost and, 2) the number of terminal profile accesses per unit time for a terminal.

This paper describes the error probability of the second order BAM estimated by a computer simulation and an analytical calculation method. The computer simulation suggests that the iterations to retrieve a library pattern almost converge within four times and the difference between once and twice is much larger than that between twice and four times. The error probability at the output of the second iteration is estimated by the analytical method. The effect of the noise bits is also estimated using the analytical method. The BAM with larger n is more robust for the noise. For example, the noise bits of 0.15n cause almost no degradation of the error probability when n is larger than 100. If the error probability of 10-4 is allowable, the capacity of the second order BAM can be increased by about 40% in the presence of 0.15n noise bits when n is larger than 500.

When the degree of intersections A B of events A, B is unknown arises a problem: how to evaluate the probability P(A B) and P(A B) from P(A) and P(B). To treat related problems two models of valuation: interval and paired probabilities are proposed. It is shown that the valuation corresponding to the set operations (intersection), (union) and (complement) can be described by the truth functional (AND), (OR) and (negation) operations in both models. The probabilistic AND and OR operations are represented by combinations of Kleene and Lukasiewicz operations, and satisfy the axioms of MV (multiple-valued logic)-Algebra except the complementary laws.

The formulation of the wall admittance of a circular microstrip antenna by the spectral domain method is presented. The circular microstrip antenna is calculated using the cavity model. The electromagnetic fields within the antenna cavity are determined from the impedance boundary condition at the side aperture. The contribution from the region outside the antenna is taken into account by the wall admittance. The wall admittance is defined by the magnetic field produced by the equivalent magnetic current at the aperture. The magnetic field is calculated by the spectral domain method. The wall admittances obtained by this method are compared with the results calculated by Shen. The calculated input impedances of the microstrip antenna agree fairly well with the experimental data for the substrate thickness of up to 0.048λg. The formulation of wall admittance presented here is easily applicable to arbitrarily shaped microstrip antennas.

We are concerned with a CDMA cellular system with unbalanced traffic environment such that a cell with high traffic should be assigned a frequency additional to the common one shared with its neighboring cells. To remove quality-dropping inter-cell hard handoffs, the cell with high traffic was first partitioned into three regions. Then, the common frequency is assigned in the outermost region, and the additional frequency is operated in the innermost region, whereas both the common frequency and the additional frequency are operated in the middle region. This frequency assignment strategy is shown not only to remove inter-cell hard handoffs without requiring extra hardware, but also to reduce intra-cell hard handoffs.

Speeding up modular inversion is one of the most important subjects in the field of information security. Over the elliptic curve -- on the prime finite field in particular goals -- public-key cryptosystems and digital signature schemes frequently use modular inversion if affine coordinates are selected. In the regular computer environment, most data transmission via networks and data storage on memories as well as the operation set of processors are performed in multiples of eight bits or bytes. A fast modular multiplication algorithm that matches these operation units for DSP was proposed to accelerate the Montgomery method by Dusse and Kaliski. However, modular inversion algorithms were developed using bit by bit operation and so do not match the operation unit. This paper proposes two techniques for modular inversion that suits any arbitrary processing unit. The first technique proposes a new extended GCD procedure without any division. It can be constructed by the shifting, adding and multiplying operations, all of which a Montgomery modular arithmetic algorithm employs. The second technique can reduce the delay time of post processing in the modular inversion algorithm. In particular, it is of great use for the modular inversion defined in the Montgomery representation. These proposed techniques make modular inversion about 5. 5 times faster.

This paper proposes a new distortion analysis method for frequency-dependent FET amplifiers, which uses a novel Frequency-Dependent Complex Power Series (FDCPS) model. This model consists of a frequency-independent nonlinear amplifier represented by an odd-order complex power series and frequency-dependent input and output filters. The in-band frequency characteristics of the saturation region are represented by the frequency-dependent output filter, while the in-band frequency characteristics of the linear region are represented by the frequency-dependent input and output filters. In this method, the time-domain analysis is carried out to calculate the frequency-independent nonlinear amplifier characteristics, and the frequency-domain analysis is applied to calculate the frequency-dependent input and output filter characteristics. The third-order intermodulation (IM3) calculated by this method for a GaAs MESFET amplifier is in good agreement with the numerical results obtained by the Harmonic Balance (HB) method. Moreover, the IM3 calculated by this method also agrees well with the measured data for an L-band 3-stage GaAs MESFET amplifier. It is shown that this method is effective for calculating frequency-dependent distortion of a nonlinear amplifier with broadband modulation signals.

In this paper, a new multicast routing method for layered streams is proposed. This method is an extension of the weighted greedy algorithm (WGA) and uses two kinds of weight values to refine the link distance. It can cope with dynamic change in the group members without multicast tree re-construction. The method is compatible with the RSVP and can be utilized in existing shared tree type routing protocols such as CBT and PIM sparse mode. The network resources can be utilized efficiently; furthermore, the loss rate of member's requests to receive more layers can be reduced by this routing method when a sufficient number of nodes have the packet filtering function and a sufficient number of hops is permitted.

The architecture and control procedure for a direct conversion receiver are investigated for a linear modulation scheme. The proposed design techniques maintain receiver linearity despite various types of signal distortion. The techniques include the fast gain control procedure for receiving a control channel for air interface connection, DC offset canceling in both analog and digital stages, and 2nd-order intermodulation distortion canceling in an analog down-conversion stage. Experimental and computer simulation results on PHS (Personal Handy-phone System) parameters, showed that required linear modulation performance was achieved and thus the applicability of the proposed techniques was demonstrated.

This paper describes amplification with improved linearity by employing a linearizing circuit in an input circuit of an internally-matched Ku-band high power amplifier. The linearizing circuit is composed of series L, C, R and an FET with grounded source and drain, and is connected between the input signal line and ground. This linearizing circuit was applied to a Ku-band 10 W output power amplifier utilizing a 25.2 mm gate-width double-doped Heterojunction FET. The power amplifier demonstrated a 8 dB reduction of the third-order intermodulation at about 6 dB output power backoff point from the 2 dB output compression point.

We propose an H-plane manifold-type triplexer with closely arranged junctions. Broadband characteristics for each bands are obtained by arranging filters closely near the end of the common waveguide. Three fundamental and sufficient parameters are introduced for numerical optimizations to determine the configuration of the broadband triplexer. The configuration including closely arranged junctions requires an generalized scattering matrix (GS matrix) of an asymmetric cross junction to simulate and design. We expand the mode matching technique (MMT) to be able to analyze this kind of discontinuities by joining two asymmetric steps discontinuities to a symmetric cross junction. This is suitable expressions for numerical calculations. The characteristics of the whole triplexer are obtained by cascading GS matrices of the corresponding discontinuities. The experimental results of the fabricated triplexer were compared with the simulated data, and the results agree well with the simulated one. The characteristics of the fabricated triplexer satisfy the request of the broad band operation and high power-handling capability.

This paper describes the distortion characteristics of an even harmonic type direct converter (EH-DC) used in earth stations for CDMA satellite communications. Direct conversion technique is known as a method to simplify circuit topologies of microwave transceivers. In satellite communications, multi carriers which have high and nearly equal level are provided to a quadrature mixer of the EH-DC. Hence, the third-order intermodulation degrades receiving characteristics. In this paper, we show the relationship between the distortion characteristics and noise figure of the EH-DC for CDMA satellite communication systems. Furthermore, we show NPR of even harmonic quadrature mixers caused by the third-order intermodulation. Experimental results in X-band indicate that the proposed EH-DC has almost the same BER characteristics compared with a heterodyne type transceiver.

Cerebellar Model Articulation Controller (CMAC) has been proposed as one of artificial neural networks. This paper describes a design scheme of intelligent control system consists of some CMACs. Each of CMACs is trained for the specified reference signal. A new CMAC is generated for unspecified reference signals, and the CMAC whose reference signal is nearest for the new reference signal, is eliminated. Therefore, since the reference signals are removed from the input signals of the CMAC, the proposed intelligent controller can be designed with fairly small memories.

This paper introduces an alternating rebound Turing machine and investigates some fundamental properties of it. Let DRTM (NRTM,ARTM) denote a deterministic (nondeterministic and alternating) rebound Turing machine, and URTM denote an ARTM with only universal states. We first investigate a relationship between the accepting powers of rebound machines and ordinary machines, and show, for example, that (1) there exists a language accepted by a deterministic rebound automaton, but not accepted by any o(log n) space-bounded alternating Turing machine, (2) alternating rebound automata are equivalent to two-way alternating counter automata, and (3) deterministic rebound counter automata are more powerful than two-way deterministic counter automata. We next investigate a relationship among the accepting powers of DRTM's, NRTM's, URTM's and ARTM's, and show that there exists a language accepted by alternating rebound automata, but not accepted by any o(logn) space-bounded NRTM (URTM). Then we show that there exists an infinite space hierarchy for DRTM's (NRTM's, URTM's) with spaces below log n. Furthermore, we investigate a relationship between the strong and weak modes of space complexity, and finally show that the classes of languages accepted by o(logn) space-bounded DRTM's (NRTM's, URTM's) are not closed under concatenation and Kleene .

In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and 3 dB bandwidth are 9.56 µW and 107 MHz, respectively. The active area of the proposed multiplier is 210 µm 140 µm.

This paper presents a new approach to designing arithmetic circuits by using a graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG). The key idea of the proposed method is to introduce a higher level of abstraction for arithmetic algorithms, in which arithmetic circuit structures are modeled as data-flow graphs associated with specific number representation systems. The EGG system employs evolutionary operations to transform the structure of graphs directly, which makes it possible to generate the desired circuit structure efficiently. The potential capability of EGG is demonstrated through an experiment of generating constant-coefficient multipliers.

This paper presents an efficient algorithm to compute the characteristic polynomial of a polynomial matrix. We impose the following condition on given polynomial matrix M. Let M0 be the constant part of M, i. e. M0 M ( mod (y,,z)), where y,,z are indeterminates in M. Then, all eigenvalues of M0 must be distinct. In this case, the minimal polynomial of M and the characteristic polynomial of M agree, i. e. the characteristic polynomial f(x,y,,z) | x E M | is the minimal degree (w. r. t. x) polynomial satisfying f(M,y,,z) 0. We use this fact to compute f(x,y,,z). More concretely, we determine the coefficients of f(x,y,,z) little by little with basic matrix operations, which makes the algorithm quite efficient. Numerical experiments are given to compare the algorithm with conventional ones.

This paper proposes a method of improving the accuracy of the attenuation constant estimate obtained by using the cross-spectral technique. In the cross-spectral technique, the envelope of the estimated impulse response is deformed due to the use of a time window. As a result, the estimated impulse response decays more rapidly than the real impulse response does, and the attenuation constant obtained by the estimated impulse response becomes larger than the real value. This paper first describes how the attenuation constant changes in the process of impulse response estimation. Next, we propose a method of improving the accuracy of the estimation. The effect of the proposed method is confirmed by computer simulation.

A model of the prefrontal cortical circuit has been constructed to investigate the dynamics for working memory processing. The model circuit is multi-layered and consists of a number of circuit modules or columns, each of which has local, excitatory and inhibitory connections as well as feedback connections. The columns interact with each other via the long-range horizontal connections. Besides these intrinsic connections, the pyramidal and spiny cells in the superficial layers receive the specific cue-related input and all the cortical neurons receive a hypothetical bias input. The model cortical circuit amplifies the response to the transient, cue-related input. The dynamics of the circuit evolves autonomously after the termination of the input. As a result, the circuit reaches in several hundred milliseconds an equilibrium state, in which the neurons exhibit graded-level, sustained activity. The sustained activity varies gradually with the cue direction, thus forming memory fields. In the formation of the memory fields, the feedback connections, the horizontal connections, and the bias input all play important roles. Varying the level of the bias input dramatically changes the dynamics of the model cortical neurons. The computer simulations show that there is an optimum level of the input for the formation of well-defined memory fields during the delay period.