This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.

This paper describes the new α-particle induced soft error mechanism, the Minority Carrier Outflow (MCO) effect, which may seriously affect the reliability of the scaled DRAMs with three dimensional capacitors. The MCO chargge increases as the device size miniaturizes because of the three dimensional capacitor effect as below. As the device scales down, the storage node volume decreases which results in the higher minority carrier density in the storage node and larger outflow charge. Also as the device plan view miniaturizes, the stack capacitor height or trench depth does not scales down or even increases to keep the storage node capacitance, therefore the initially generated minority carrier becomes larger. A simple analytical MCO model is introduced to evaluate the MCO effect quantitatively. The model agrees well with the three dimensional device simulation. The MCO model predicts that the life time of the minority carrier in the storage node strongly affects the MCO charge, however, even when the life time is as small as the order of 100 ps, the MCO effect can be the major soft error mechanism.

The goal of this paper is to propose a new symbolic model checking approach named time-space modal model checking, which could be applicable to verification of bit-slice microprocessor of infinite bit width and one dimensional systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

New multimedia applications have emerged on top of information infrastructures, such as on-demand services, digital libraries and museums, online shopping, information Q & A, concurrent engineering, document management, and desktop program production, which require new databases. That is, next-generation database systems must enable users to efficiently and flexibly develop and execute such advanced multimedia applications. Moreover, in some applications, there is no existent data; in others, there are databases or files to be integrated. This requires both top-down and bottom-up database development. To this end, we focus on development of a database system which enables flexible and efficient acquisition, storage, access and retrieval, and distribution and presentation of large amounts of heterogeneous media data. In particular, we propose a multimedia data model as an integration of structural, temporal, spatial, and control functionality. That is, we take an approach based on an object-oriented database, which is more suitable for description of media structures and operations than a traditional relational database. And we extend the object-oriented approach by providing temporal and spatial operators, and control of distributing computing and QOS (quality of service). In this paper, we describe a multimedia data model and its efficient implementation.

The global interpolation method we propose evaluates segment pattern continuity and connectedness to produce characters with smooth edges while interpreting blank or missing segments based on global label connectivities, e.g, in extracting a handwritten character overlapping a border, correctly. Conventional character segmentation involving overlapping a border concentrates on removing the thin border based on known format information rather than extracting the character. This generates discontinuous segments which produce distortion due to thinning and errors in direction codes, and is the problem to recognize the extracted character. In our method, characters contacting a border are extracted after the border itself is labeled and removed automatically by devising how to extract wavy and oblique borders involved in fax communication. The absence of character segments is then interpolated based on segment continuity. Interpolated segments are relabeled and checked for matching against the original labeled pattern. If a match cannot be made, segments are reinterpolated until they can be identified. Experimental results show that global interpolation interprets the absence of character segments correctly and generates with smooth edges.

There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.

A method to design one-dimensional cellular arrays to be used as TPG circuits of BIST is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximum cycles are derived based on fast parallel implementations of LFSRs.

Conformance testing techniques are required for the efficient production of reliable communication protocols. A lot of conformance testing techniques have been developed. However, most of them can only decide whether an implemented protocol conforms to its specification. That is, the exact locations of faults are not determined by them. This paper presents some conditions that enable to find locations of multiple faults, and then proposes a test sequence generation technique under such conditions. The correctness proof and complexity analysis of the proposed technique are also given. The characteristics of this technique are to generate test sequences based on protocol specifications and interim test results, and to find locations of multiple faults in protocol implementations. Although the length of the test sequence generated by the proposed technique is a little longer than the one generated by the previous one, the class to which the proposed technique can be applied is larger than that to which the previous one can be applied.

A test system with a fuzzy logic controller is proposed to assure stable outgoing quality as well as to raise throughput. The test system controls the number of items under test in accordance with fuzzy information as well as statistical information about incoming quality and outgoing quality. First, an algorithm, minimum-minimum-the center of gravity-weighted mean method, is studied with both fuzzy reasoning rules and membership functions which are used for the control. Second, characteristics of the test system are verified and examined with computer simulations so that the fuzzy logic control rules are determined to realize sufficient sensitivity to process changes. Third, the control rules are installed in the test management processor which commands test equipment for testing very large scale integrated circuits, with programming language C. The authors have obtained satisfactory results through a trial run using a series of lots of 16 bit micro controller units in an IC manufacturing factory. Finally, they study the stability condition of the fuzzy test system.

This paper describes analytical results of high-Tc superconducting asymmetric coplanar strip lines using the frequency-dependent finite-difference time-domain method. The propagation constants of the YBa2Cu3O7-x asymmetric coplanar strip line fabricated on the LiNbO3 substrate are reported. The effect of the SiO2 buffer layer is also investigated.

Recently, through high speed computer networks, multifarious information such as text, moving and still images, video, voice and control data is available. There is a natural demand to store such multimedia data in databases to facilitate their reuse in a wide variety of applications. Therefore, important research issues pertain to the investigation of appropriate database systems in multimedia computer network environments. In this paper, we first discuss the required technologies for multimedia information systems. Then we look at many multimedia information services through computer networks, and consider the importance of storing and effectively reusing such available multimedia data. To facilitate developing databases for use in these environments, we discuss the evolution of the notion of database systems. Finally, we demonstrate, as practical examples of such database systems, two prototype systems that we are currently implementing, i.e., the campus wide news on demand system and the ASN. 1 database system.

Currently there is considerable world-wide speculation regarding the introduction of optical fiber cable into access networks, because optical fiber has a big potential for providing attractive multimedia services. Since optical fiber cable can provide a variety of grade of services, high-reliability of cable networks would be required compared with the conventional copper cable networks. To develop multimedia telecommunication networks as an infrastructure, it is urgent to clarify the highly reliable optical fiber cable network architecture. Since cable network architecture deeply depends on regional conditions such as demand, area size, duct layer networks (consisting of ducts, manholes, tunnels, feeder points etc.), it is necessary to develop a cable network designing tool with user-friendly interfaces for efficiently evaluating cable network architectures. This paper firstly proposes the heuristic algorithms enhanced by the disjoint-shortest-path and the depth-first-search methods that would be applicable for real access networks. Secondly, the design method of highly reliable optical fiber cable network based on the heuristic algorithms in terms of network cost and unavailability caused by cable breakdown is proposed. It can design the combination of star- and loop-shaped (where two diversified routes exist between a feeder point and central office) cable network. Furthermore, comparison with the conventional design method which simply applies star- or loop-shaped cable network is done in terms of economy and reliability on real access networks in the Tokyo metropolitan area. It is concluded that the proposed method can reduce the network cost further and realize a short unavailability value compared with the conventional method.

This paper presents the concept of k-FR circuits. The controllability of such a circuit is high due to its special structure. It is shown that all stuck-at faults and stuck-open faults in a k-FR circuit can be detected and located by k(k1)1 test vectors under the highly observable condition which assumes the output of every gate to be observable. k is usually two or three. This paper also presents an algorithm for converting an arbitrary combinational circuit into a k-FR circuit. A k-FR circuit is easy to test when using technologies such as the electron-beam probing, the current measurement, or the CrossCheck testability solution.

This paper deals with the problems in testing large mixed-signal ICs. To help generating test patterns of these larger mixed-signal circuits for a functional test, a fast fault simulation algorithm and a fault model voltage stuck-at fault" which the algorithm is based on, are proposed. A voltage stuck-at fault is that a signal line sticks its voltage level at a certain constant. Under an assumption that blocks in a circuit are designed as identically current-independent, i.e. their input impedance can be regarded as infinite and their output impedance as zero, fault simulation can be realized by the event driven method and the concurrent method and can detect voltage stuck-at faults. These methods are essential for digital fault simulation and very effective to high speed simulation, although they were impossible for an analog or mixed-signal circuit by a conventional algorithm. Furthermore, the efficiency of the simulation is improved because I/O relation of blocks is approximated to a stepwise linear function. The above techniques and methods make fault simulation for a mixed-signal circuit possible in practical use. Actually, a fault simulator was implemented, then some test circuits were simulated. The simulator is really faster than conventional simulation based on circuit simulation. Next, fault analysis was applied to several bipolar ICs to verify the validity of the fault model voltage stuck-at faults". Analyses of open and short faults between terminals of transistors and resistors show that this fault model has sufficient coverage (more than 50%) to test mixed-signal circuit.

Synchronization of media streams is recognized as an important requirement not only in media retrieval such as a video on-demand service but also in groupware such as a remote conferencing system. In a remote conferencing system, synchronization is more complicated because Live Media Streams (LMS) such as the live raw voice of some participants must be taken into consideration as well as Retrieved Media Streams (RMS) such as media streams retrieved from video equipment. In this paper, we propose a mechanism to synchronize RMSs and LMSs in a remote conferencing system DMSIC (Distributed Multimedia System with Interactive Control) which has been implemented on UNIX workstations connected by Ethernet. In this mechanism, synchronization among RMSs (we call it R & R synchronization) is kept by maintaining the Current Presentation Positions (CPP) on Media Buffers (MB) close to the Ideal Presentation Position (IPP). Synchronization among RMSs and LMSs (we call it R & L synchronization) is kept by adjusting the IPPs among multiple nodes. We have implemented the synchronization mechanism in DMSIC to confirm the effectiveness of it.

At the beginning of the 21st century, 1 Gb DRAMs will be in practical use, and sufficient in terms of memory capacity for most memory applications systems. The key technologies for multimedia systems include data compression, communication, storage, and human interfaces. Image data processing, ATM switch, and microprocessor in multimedia applications require the high data transfer rate from several 100 Mbits/s to Tbits/s. Storage systems, on the other hand, require the reduction of the price per bit to less than 10 cents/Mbytes. Application specific design approaches towards a system-on-chip are strongly needed for ULSI memories in the multimedia era.

This paper discussed a distributed processing architecture for a virtual space teleconferencing system. Virtual space teleconferencing is a promising application field for networked virtual environments. People in different places will be able to meet each other in a virtual teleconferencing room and proceed with various cooperative tasks. When such a system creates a realistic virtual environment, it can be referred to as a "Teleconferencing with realistic sensations" system. Further more, as the conference environment can be shared by a number of users, it is possible to perform various kinds of cooperative work using the system. In this paper, the architecture for networked multi-user virtual space systems are classified, and then a case study is described for building a proposed teleconferencing system. The system reproduces a 3D image of each conference participant in a virtual meeting room. Compared with the former system, the new system can deal with more than three participants at the same time and can connect them through commercial telephone lines. Based on the virtual world database management structure, the system was classified as a central server system. However, a central server architecture limits the number of conference sites. We confirmed that the system can serve up to 14 sites using multi-modal interaction without significant latency in operation from summational experiments. Then, introducing some assumptions to the results, we have proposed processing model of the system. The results of model could describe the experimental results and we could indicate roughy estimated system capacity to realize a requaied system performance.

This paper gives several explicit formulas for the waiting times in each stage in an alternating-service, two-stage tandem queue (M/G/1 type queue) with a gate in the first stage and server vacations (or setup time). These formula are obtained by using simple conversion relationships between the performance measures. This study has been motivated by the performance evaluation of call (packet or message) processing in telecommunication switching systems.

This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.

Multimedia communication services are being made available with the advent of broadband optical fiber networks. As many different services will be accommodated in such networks, network survivability has been recognized to be a crucial concern. In this paper, we propose a new restoration algorithm for ATM networks providing multimedia services. Our proposed restoration algorithm adopts the message bundling scheme of the Multi-Destination Flooding (MDF) algorithm which was previously proposed for STM-based networks to handle catastrophic failures such as multiple link and node failures. Virtual Paths (VP) with the same communication speed are bundled and Operation Administration and Maintenance (OAM) cells are used for communication of restoration messages. In addition, the following modifications are made on the original MDF to improve restoration performance. The pre-cancellation scheme is adopted to arbitrate reservation contention to realize high restoration ratio. The dual queue scheme is applied to avoid congestion of restoration messages. Moreover, the connection control scheme for VPI connections is proposed to prevent alternative routes from being misconnected. This paper describes the design concept of our restoration algorithm, processes in each restoration phase, and the performance evaluation by computer simulation.