We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.

The recent rapid increase in the scale of superconducting quantum computing systems greatly increases the demand for qubit control by digital circuits operating at qubit temperatures. In this paper, superconducting digital circuits, such as single-flux quantum and adiabatic quantum flux parametron circuits are described, that are promising candidates for this purpose. After estimating their energy consumption and speed, a conceptual overview of the superconducting electronics for controlling a multiple-qubit system is provided, as well as some of its component circuits.

CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.

The single flux quantum (SFQ) is expected to be a next-generation high-speed and low-power technology in the field of logic circuits. CMOS as the dominant technology for conventional processors cannot be replaced with SFQ technology due to the difficulty of implementing feedback loops and conditional branches using SFQ circuits. This paper investigates the applicability of a reconfigurable data-path (RDP) accelerator based on SFQ circuits. The authors introduce detailed specifications of the SFQ-RDP architecture and compare its performance and power/performance ratio with those of a graphics-processing unit (GPU). The results show at most 1600 times higher efficiency in terms of Flops/W (floating-point operations per second/Watt) for some high-performance computing application programs.

We present our design and operation of a 6-bit quasi-triangle voltage waveform generator comprising three circuit blocks; an improved variable Pulse Number Multiplier (variable-PNM), a Code Generator (CG), and a Double-Flux-Quantum Amplifier (DFQA). They are integrated into a single chip using a niobium Josephson junction technology. While the multiplication factor of our previous m-bit variable-PNM was limited between 2m-1 and 2m, that of the improved one is extended between 1 and 2m. Correct operations of the 6-bit variable-PNM are confirmed in low-speed testing with respect to the codes from the CG, whereas generation of a 6-bit, 0.20mVpp quasi-triangle voltage waveform is demonstrated with the 10-fold DFQA in high-speed testing.

We describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.

We propose a neutron diffractometer system based on MgB2 thin film detectors and an SFQ signal processor. Small dimensions of MgB2 thin film detectors and high processing capability of the single flux quantum (SFQ) circuits enable us to handle several thousand or more detectors in a cryocooler, leading to a very compact system. In addition, the system can provide many diffraction patterns for different kinetic energies simultaneously. Kinetic energy is determined for individual neutrons by means of the time-of-flight method by using SFQ time-to-digital converters (TDCs). Digital outputs of the TDCs are multiplexed in time domain and sent to room-temperature electronics with reduced number of cables. A dual-input SFQ signal processor including TDCs and a multiplexer has been successfully demonstrated with a time resolution of 20 ns and power consumption of 400 µW. These values show high feasibility of the neutron diffraction system proposed here.

A single flux quantum (SFQ) logic cell library has been developed for the 10 kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm2 to 10 kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

Ultra fast switching speed of superconducting digital circuits enable realization of Digital Signal Processors with performance unattainable by any other technology. Based on rapid-single-flux technology (RSFQ) logic, these integrated circuits are capable of delivering high computation capacity up to 30 GOPS on a single processor and very short latency of 0.1 ns. There are two main applications of such hardware for practical telecommunication systems: filters for superconducting ADCs operating with digital RF data and recursive filters at baseband. The later of these allows functions such as multiuser detection for 3G WCDMA, equalization and channel precoding for 4G OFDM MIMO, and general blind detection. The performance gain is an increase in the cell capacity, quality of service, and transmitted data rate. The current status of the development of the RSFQ baseband DSP is discussed. Major components with operating speed of 30 GHz have been developed. Designs, test results, and future development of the complete systems including cryopackaging and CMOS interface are reviewed.

This paper presents the history of superconductor digital circuits starting from several years after the discovery of the Josephson junction in 1962. The first two decades were mainly devoted to developing voltage-state logic, which is similar to semiconductor logic. Research on circuits employing the manipulation of single magnetic flux quanta resulted in a form called RSFQ in the mid-1980s; this is the basis of superconductor logic systems of today. The more difficult problem of random access memory is reviewed. We analyze the present status of the field and outline the work that lies ahead to realize a successful superconductor digital technology.

A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40 GHz, and the demonstration of a 47-Gbps SFQ 22 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4 K with a two-stage 1-W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (~10 Gbps/ch) and SFQ circuits (>40 GHz). An SFQ 22 switch chip, in which the MUX/DEMUX and an SFQ 22 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10 kA/cm2. An SFQ 22 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with φ 50-µm InSn solder bumps. An SFQ 22 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47 Gbps for the first time.

We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4 mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.

We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-Tc single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating ramp-edge Josephson junctions with IcRn products above 1 mV at 40 K and small Ic spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the Jc spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200 GHz at 40 K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-Δ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100 GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50 GHz.

We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 11 µm, a line width of 0.8 µm, a JJ critical current density of 10 kA/cm2, a 2.4 Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120 GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.

Single flux quantum (SFQ) circuit elements have been designed and fabricated using the YBa2Cu3O7-δ ramp-edge junction technology. Logic operations of SFQ circuit elements, such as a toggle flip-flop (T-FF), a set-reset flip-flop (RS-FF), and a 96-junction Josephson transmission line (JTL), were successfully demonstrated, and dc supply current margins were confirmed up to temperatures higher than 30 K. The circuit layout was improved in order to suppress the critical current (Ic) spread that appears during the junction fabrication procedure. By employing the new circuit layout rule, correct operations at temperatures from 27 K to 34 K with dc supply current margins wider than 7% were confirmed for the T-FF with a single output. Moreover, the maximum operating frequencies of T-FFs were measured to be 360 GHz at 4.2 K and 210 GHz at 41 K, which are substantially higher than the values for the circuits with the conventional layout. According to the simulation result, the maximum operating frequency at 40 K was expected to be approximately 50% of the characteristic frequency at a bit error rate (BER) less than 10-6.

In this paper, we describe two approaches to optimize the Phase-Mode pipelined parallel multiplier. One of the approaches is reforming a data distribution for an AND array, which is named the hybrid structure. Another method is applying a Booth encoder as a substitute of the AND array in order to generate partial products. We design a 2-bit 2-bit Phase-Mode Booth encoder and test the circuit by the numerical simulations. The circuit consists of 21 ICF gates and operates correctly at a throughput of 37.0 GHz. The numbers of Josephson junctions and the pipelined stages in each scale of multipliers are reduced remarkably by using the encoder. According to our estimations, the Phase-Mode Booth encoder is the effective component to improve the performance of large-scale parallel multipliers.

The capability of a high-temperature superconducting sigma-delta modulator was studied by means of circuit simulation and FFT analysis. Parameters for the circuit simulation were extracted from experimental measurements. The present circuit simulation includes thermal-noise effect. Successive FFT analyses were made to evaluate the dynamic range of the sigma-delta modulator. As a result, the dynamic range was evaluated as 60.1 dB at temperature of 20 K and 56.9 dB at temperature of 77 K.

Analysis of the operation modes of an RF-Field-Driven DC-SQUID (RFDS) is presented. We numerically calculate the current-voltage characteristics (IVC) of the RFDS, where the RF signal is coupled to the SQUID loop magnetically. Under no DC offset flux, the IVC exhibit the enhancement of the even-order steps. We first evaluate the dependence of the maximum 2nd step height of the RFDS upon frequency. Contrary to the results for a single junction, the RFDS maintains its step height at a certain value in the low frequency region. The maintained values of the maximum step height are dependent on βL. The smaller βL is, the larger the maximum step height becomes. Next, we evaluate the dependence of the current positions of the 2nd step upon the amplitude of the RF signal. Under the low frequency condition, the current positions agree with the interference patterns of the SQUID, which means that the operation of the RFDS is based on the quantum transitions in the SQUID loop. Under the high frequency condition, on the other hand, the current positions agree with the results for the single junction, which means that the quantum transitions does not follow the RF signal and that the RFDS behaves like a single junction.

We investigated single flux quantum sinc filters with multistage decimation structure in order to realize high-speed sinc filter operation. Second- and third-order (k=2, 3) sinc filters with a decimation factor N=2 were designed and confirmed their proper operations. These sinc filters with N=2 are utilized as elementary circuit blocks of our multistage decimation sinc filters with N=2M, where M indicates the number of the stage of the decimation. As an example of the multistage decimation filter, we designed a k=2, N=4 sinc filter which was formed from a two-stage decimation structure using k=2, N=2 sinc filters, and confirmed its proper operation. The k=2, N=4 sinc filter consisted of 1372 Josephson junctions with the power consumption of 191 µW.