A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

In this paper, two types of improved CMRR CMOS OAs, N type and P type, without common-mode feedback and the cascode current mirrors, are proposed. The CMRR of proposed OAs are enhanced by compensating variations in tail bias current, caused by a common mode input signal, at the differential input stage, by means of feedforward controlled current source. Simulation results show that the CMRR of the proposed OAs are 20dB higher than that of conventional OAs.

In recent years, and increasing number of studies have been reported regarding multimedia LANs that integrate voice, data and video communications. The Movable Boundary method has been suggested as a way to integrate circuit and packet switching. However, how this can be practically managed, especially for multimedia LANs, is not clear. Working under the assumption that an optical loop network in used as a multimedia LAN, we propose Hybrid Allocation as a new Movable Boundary method. Hybrid Allocation features traffic prediction for circuit switching calls, and timeslot allocation close to the boundary of circuit and packet switching areas. Evaluations of traffic simulation and network efficiency show it to be a promising architecture for integrating circuit and packet switching on a multimedia LAN.

A wavelength tunable DBR laser monolithically integrated with an EA-modulator as a WDM system light source was fabricated by selective area MOVPE growth. The lasing wavelength and band-gap energy were simultaneously controlled on the same epitaxial wafer by using a modulated grown thickness of InGaAsP/InGaAsP MQW layers. A wavelength tuning range of 3.5 nm, an output power of 3 mW, and an extinction ratio of 14 dB for 3 V were achieved. The measured 3 dB frequency bandwidth was 2 GHz. No significant change in modulation characteristics were observed when wavelength tuning by injecting the current into the DBR.

Two high output-resistance CMOS current mirrors suitable for a low-voltage operation and achieving a high output-swing are presented. They incorporate a modified regulated-cascode, which employs a current-mode amplifier. The main architecture concepts and their detailed schematic examples are discussed. SPICE simulation comparison is shown and the properties of each architecture are pointed out.

As a low-cost optical transceiver for access network systems, we propose a new monolithic transceiver photonic integrated circuit (PIC) fabricated by bandgap energy controlled selective metalorganic vapor phase epitaxy (MOVPE). In the PIC, all optical components are monolithically integrated. Thus, the number of optical alignment points is significantly reduced and the assembly costs of the module is decreased compared to those of hybrid modules, that use silica waveguides. Moreover, by using selective MOVPE, extremely low-loss buried heterostructure waveguides can be fabricated without any etching. In-plane bandgap energy control is also possible, allowing the formation of active and passive core layers simultaneously without complicated fabrication. The transceiver PIC showed fiber-coupled output power of more than 1 mW and receiver bandwidth of 7 GHz. Modulation and detection operations at 500 Mb/s were also demonstrated. As a cost effective fabrication technique for monolithic PICs, bandgap energy controlled selective MOVPE is a promising candidate.

In order to highlight a rapid progress attained in the field of millimeter waves in Japan, this paper describes several key topics including transistors, integrated circuits, planar antennas, millimeter wave photonics, and others.

Because 60 GHz frequency band has been allotted for the research and development purpose of millimeter wave systems in Japan, various circuit components and systems have been fabricated by using printed transmission lines. The NRD guide (nonradiative dielectric waveguide) is another candidate as a transmission medium for millimeter wave integrated circuit applications since its performance has been shown to be excellent in this frequency band. This paper is concerned with the development of a 60 GHz digital transceiver for millimeter wave LAN use based on NRD guide technologies. The trans-ceiver consists of frequency stabilized Gunn oscillator, circulator, PIN diode modulator, balanced mixer, directional coupler and transmitting and receiving pyramidal horn antennas. The notable advantages of the circuit components are the high reliability of the Gunn oscillator, the wide bandwidth of the circulator, and the high frequency operation of the PIN diode modulator beyond 100 Mbps. Interference between transmitted and received signals, which must be caused by coupling between transmitting and receiving antennas, is eliminated by simple techniques such as introducing filters in the base band and IF circuits. By using NRD guide digital transceivers, both-way data transmission between two computers can be achieved simultaneously and a 60 GHz wireless LAN system has been developed successfully.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

For high frequency video signals, display monitors for personal computers are required to shift from the horizontal scanning frequency fH=15.75 kHz for conventional TV broadcasting to fH=64 to 80 kHz, which is called XGA. Shifting to high frequencies and restrictions on the withstand voltage of horizontal transistors decrease the inductance of deflection yokes, which is an obstacle in manufacturing deflection yokes. A study was undertaken on an operation to permit deflection/high voltage integrated operation while keeping the inductance of the deflection yoke high. This paper reports the results.

This paper describes a narrow pass-band optical filter utilizing a wavelength-sensitive power-transfer characteristic in the directional coupler composed of the K-and Ag-ion exchange waveguides which have greatly different dispersion relations caused by the large mismatch in the index profile of the waveguide cross-section. A narrow pass-band width of about 7 nm is measured in the filter fabricated in the soda-lime glass substrate. The fabrication technique with two-step ion-exchange of the K-and Ag-ions, is also presented together with a quick design method.

This paper presents an overview of research activities in Japan in the field of very low bit-rate video coding. Related research based on the concept of "intelligent image coding" started in the mid-1980's. Although this concept originated from the consideration of a new type of image coding, it can also be applied to other interesting applications such as human interface and psychology. On the other hand, since the beginning of the 1990's, research on the improvement of waveform coding has been actively performed to realize very low bit-rate video coding. Key techniques employed here are improvement of motion compensation and adoption of region segmentation. In addition to the above, we propose new concepts of image coding, which have the potential to open up new aspects of image coding, e.g., ideas of interactive image coding, integrated 3-D visual communication and coding of multimedia information considering mutual relationship amongst various media.

This paper concerns optimized facility design for VLSI production. The methods proposed are applicable in planning LSI production facilities with a good balance between the number of machines and the number of operators. The sequence in each processing step is analyzed in detail. A new algorithm based on the queueing model is developed for estimating the simultaneous requirements for the two kinds of resources, machines and operators. This estimation system can be applied to complicated fabrication schemes, such as batch processing, continuous processing, and mixed technologies. This methodology yields guidelines for ASIC LSI production system design.

A new current-mode analog BiCMOS multiplier/divider circuit based on the translinear principle is presented. This circuit can be implemented by a standard 0.8µm BiCMOS process. The simulation results showed that the circuit realizes the high-speed and high-precision operation with a 3V supply.

This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.

Discrete-time chaotic circuits realizing a tent map and a Bernoulli map are synthesized using switched-current (SI) techniques. For these proposed circuits, simulations are performed concerning the return maps and bifurcation trees. The theoretical analysis is carried out to predict the bifurcation tree under the existence of the nonidealities in the return map. This analysis has been done by assuming the return maps to be piecewise linear. The proposed circuits are built with commerciallyavailable IC's. And their return maps and bifurcation trees are measured in the experiment. The design formulas are obtained for the bifurcation trees and they are confirmed by the simulation results. The proposed circuits are integrable by a standard BiCMOS technology.

The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.

ElectroStatic Discharge (ESD) testing of integrated circuits subjects circuit elements to very high currents for short periods of time. A modified Transmission Line Pulse (TLP) measurement system for characterizing transistors and other circuit elements under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure leakage. For the TLP system to yield useful information test structures are needed which vary the important design parameters for the circuit elements. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great dfficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm9.09 mm die. It can realize an 11.2 kbps VSELP speech CODEC while consuming only 70 mW at 3.5 V Vdd.