A novel phase compensation technique for feedback integrators is proposed. By the technique, a zero is obtained without employing extra capacitors. A design of an integrator for IC using the proposed technique is presented. The frequency of the parasitic pole is proportional to the unity gain frequency. It is shown that excess-phase cancellation is obtained at any unity gain frequency.

The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.

This paper examines the design considerations for an opamp to be used in a low-power consumption LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The experimental results support our opamp design approach and indicate the feasibility of a 10 µA quiescent current opamp.

An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

This study shows the results of evaluating the flux noises at low frequency when the alternating current(AC) bias direct offset integrated technique(DOIT) with additional positive feedback (APF) is used in a high-Tc dc superconducting quantum interference device (SQUID). The AC-bias DOIT can reduce low-frequency noise without increasing the level of white noise because each operating point in the two voltage-flux characteristics with AC bias can always be optimum on the magnetometer in the high-Tc dc-SQUID. APF can improve the effective flux-to-voltage transfer function so that it can reduce the equivalent flux noise due to the voltage noise of the preamplifier in the magnetometer. The use of APF combined with the AC-bias DOIT reduced the noise of the magnetometer by factors of 1.5 (33µΦ0/Hz vs. 50 µΦ0/Hz) at100 Hz, 3.5 (43 µΦ0/Hz vs. 150 µΦ0/Hz) at 10 Hz, and 5.2 (67 µΦ0/Hz vs. 351 µΦ0/Hz) at 1 Hz as compared with the noise levels that were obtained with the static-current-bias DOIT. The contribution of the factors at 1 Hz is about 2 by APF and 2.6 by AC bias. The performance of improving the flux noise in the AC -bias DOIT with APF is almost equal to that of the flux locked loop (FLL) circuits in which the flux modulation uses a coupling system with a transformer and with the AC bias.

This is a review of our high-Tc superconductor (HTS) sampler development. The design and experimental demonstration of a Josephson sampler circuit based on YBa2 Cu3Ox(YBCO)/PrBa2Cu3Ox/YBCO ramp-edge junctions is described. The sampler circuit contains five edge junctions with a stacked YBCO groundplane and is based on single-flux quantum (SFQ) operations. Computer simulation results show that the time resolution of the sampler circuit depends strongly on the IcRn product of the junction and can be reduced to a few picoseconds with realistic parameter values. The edge junctions were fabricated using an in-situ process in which a barrier and a counter-electrode layer are deposited immediately after the edge etching without breaking the vacuum. The in-situ process improved the critical current uniformity of the junctions to 1σ20% in twelve 4-µm-width junctions. An YBCO groundplane was placed on the junctions in a multilayer structure we call the HUG (HTS cricuit with an upper-layer groundplane) structure. The inductance of YBCO lines was reduced to 1 pH per square without junction-quality degradation in the HUG structure. SFQ current-pulse generation, SFQ storage, and SFQ readout in the circuit have been confirmed by function tests using 3-kHz pulse currents. The successful operation of the sampler circuit has been demonstrated by measuring a signal-current waveform at 50K.

In this work, the performance evaluation of a voice and data integrated fast PRMA has been done. In this newly proposed protocol, every data terminal has an infinite buffer and voice terminals can work independently of data terminals. Thus voice terminals have the higher priority over data terminals. We can, therefore, analyze voice and data subsystems separately. For voice analysis, we use a Markov analysis, and we use the EPA method for data analysis in order to create an analytic form. As performance measures, the voice packet dropping probability, the average voice and data delays, and the total throughput have been derived. It is shown how many voice and data terminals the fast PRMA protocol can accommodate in a frame under the constraints that the voice packet dropping probability should be less than 0.01, and average data packet delay should be less than 250 msec. We also discuss the stable region for this system. Numerical results show close agreement between analysis and computer simulation.

This paper proposes the use, in integrated wireless systems, of the Reserved Idle Signal Multiple Access with Collision Resolution (R-ISMA/CR) protocol for applications in future multimedia mobile communications. It is applied to the integrated voice and data wireless system. Moreover, the consideration is made of the integrated voice and the low-bit video wireless system in R-ISMA/CR. To integrate video we employed not only a packed discard for video packets when the video packet delay is more than a threshold value, but also the connection packet (CP) technique for improving the channel utilization. Finally the integration of voice, data, and low-bit-video wireless system in R-ISMA/CR is considered. The performance are evaluated mainly by simulations.

It is highly desirable to develop an efficient and flexible dynamic channel assignment algorithm in order to realize an integrated traffic TDMA mobile radio communication network. In this paper, an integrated traffic TDMA system is studied in which transmission of voice and data are assumed to occupy one and n time slots in each TDMA frame, respectively. In general, there are two types of channel (time slot) assignment algorithms: the partitioning algorithm and the sharing algorithm. However, they are not well-suited to the multimedia traffic consisting of various information sources that occupy different number of slots per frame. In this paper, assuming that voice is much more sensitive to transmission delay than data, an algorithm based on the sharing algorithm with flexible tima slot management scheme is proposed. Our method tries to vary the number of data slots adaptively so as to improve the quality of servive of voice calls and the system capacity. Computer simulations show the good performance of the proposed algorithm when compared to conventional channel assignment algorithms.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.

This paper describes a concept of the quasioptical spatial power combining technique and its demonstration of active integrated antenna arrays with strong coupling as an actual example of high efficient combiner in high frequencies. Some configurations of the arrays such as a 3-element linear array and a 33 array are designed with a circuit and electromagnetic simulator. In order to predict the operating frequencies, large signal FET model parameters are determined from measured small signal S-parameters.

Private networks are becoming globalized and more complicated through LAN-WAN interconnection. While WANs are managed by CMIP, LANs are managed by SNMP. To achieve end-to-end management, the integration of CMIP-based and SNMP-based management is important. We have developed an MI (Management Integration) platform for CMIP-based and SNMP-based management. It provides OSI SMF (Systems Management Function)-based unified basic management services to upper level applications regardless of the differences between CMIP-based and SNMP-based management. It achieves this with two modules: a management information transfer integration module that mainly covers protocol and data format differences between them, and a basic management module that covers functional differences. The translation of management information in the former module can be changed flexibly because the translation is based on an external script file. The latter module has additional SMF-like functions for the management of SNMP agents in addition to SMF manager role functions, etc. Prototype evaluation has demonstrated the feasibility of the MI platform.

There is now a world-wide trend towards the downsizing of information systems using a number techniques, such as clientserver architecture. Consequently, enterprise networks are fast growing in terms of size and functionality. These networks need to be managed effectively. Researchers have been working on the development of management solutions for enterprise networks, using recent advances in software engineering, communication protocols, and artificial intelligence techniques. However, not much work has been published on the role of human factors in the integrated management of networks and systems. This paper presents a new Cooperative management Methodology for Enterprise Networks (CoMEN), based on Computer Supported Cooperative Work (CSCW) techniques.

As enterprises use ATM networks for their private networks and as these private networks use public ATM networks for wide area communication, the need for the customers to be able to manage both private and public networks is increasing. Currently, some standardization work is being done towards providing this capability to customers. In this paper, we propose a new customer network management (CNM) system architecture for the management of both private and public ATM networks in a uniform way. The particular features of the proposed architecture lies in the efficient support of the complex hierarchical TMN manager-agent relationships at M3 and M4 interfaces, and the support of SNMP and CMIP integration. The TMN hierarchical many-to-many manager-agent relationships are realized by the utilization of a CORBA-based Shared Management Knowledge (SMK) system. We have implemented a prototype of ATM CNM system, and measured the performance for the demonstration of the suitability of the proposed architecture.

Our compact switching converter using a thin-film microtransformer mono-lithically integrated with rectifier diodes represents the first step in developing a monolithic micro-switching converter that can be integrated with semiconductor devices and magnetic components. This converter is a single-ended forward converter with resonant reset and operates successfully at 15 MHz. The maximum output power is 0.5 W.

This paper describes the analysis of integrated optical waveguides using Finite-Difference Time-Domain (FDTD) method, and proposes the design methodology for low loss waveguide components: corner bends and branches. In order to integrate optical waveguides with Si VLSI technologies on a chip, the compact bends or branches are necessary. Since the optical power radiation from a bend or a branch point depends on the waveguide shapes, an accurate analysis of guided wave behavior is required. For the purpose we adopted the FDTD method which can analyze optical waveguides with a large variation of refractive index and arbitrary shape. Proposed design concept is to have all waveguides transmit only the fundamental mode and to design whole waveguides based on the fundamental mode transfer characteristics. For this design concept, waveguide components are required to have not only low radiation loss but also a little mode shift from the fundamental mode. The bend using the double-reflection mirrors and the branch using a slit are proposed for suppressing the mode shift and improving radiation loss. By the FDTD analysis, the following results have been obtained. The radiation loss and mode shift of double reflection bend are 1% and 4%, and those of the slit branch are 2% and 5%, respectively, in 2 µm width waveguide.

A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

Photonic integrated circuits (PICs) are required for future optical communication systems, because various optical components need to be compactly integrated in one-chip configurations with a small number of optical alignment points. Bandgap energy controlled selective metal organic vapor phase epitaxy (MOVPE) is a breakthrough technique for the fabrication of PICs because this technique enables the simultaneous formation of waveguides for various optical components in one-step growth. Directly formed waveguides on a mask-patterned substrate can be obtained without using conventional mesa-etching of the semiconductor layers. The waveguide width is precisely controlled by the mask pattern. Therefore, high device uniformity and yield are expected. Since we proposed and demonstrated this technique in 1991, various PICs have been reported. Using electroabsorption modulator integrated distributed feedback laser diodes, 2.5 Gb/s-550 km transmission experiments have been successfully conducted. Another advantage of the selective MOVPE technique is the capability to form narrow waveguide layers. We have demonstrated a polarization-insensitive semiconductor optical amplifier that consists of a selectively formed narrow (less than 1 µm wide) bulk active layer. For a four-channel array, a chip gain of more than 20 dB and a gain difference between TE and TM inputs of less than 1 dB were obtained. We have also reported an optical switch matrix and an optical transceiver PIC for access optical networks. By using a low-loss optical waveguide, a 0 dB fiber-to-fiber gain for the 14 switch matrix and 0 dBm fiber output power from the 1.3 µm transceiver PIC were obtained. In this paper, the selective MOVPE technique and its applications to various kinds of PICs are discussed.