This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

Artificial Neural Networks (ANN's) that are able to learn exhibit many interesting features making them suitable to be applied in several fields such as pattern recognition, computer vision and so forth. Learning a given input-output mapping can be regarded as a problem of approximating a multivariate function. In this paper we will report a theoretical framework for approximation, based on the well known sequences of functions named approximate identities. In particular, it is proven that such sequences are able to approximate a generally continuous function to any degree of accuracy. On the basis of these theoretical results, it is shown that the proposed approximation scheme maps into a class of networks which can efficiently be implemented with analog MOS VLSI or BJT integrated circuits. To prove the validity of the proposed approach a series of results is reported.

Characterization of silicon devices incorporating the capacitor which uses ferroelectric thin films as capacitor dielectrics is presented. As cases in point, a DRAM cell capacitor and an analog/digital silicon IC using the thin film of barium strontium titanate (Ba1-xSRxTiO3) are examined. Production and characterization of the ferroelectric thin films are also described, focusing on a Metal Organic Deposition technique and liquid source CVD.

The increasing size and complexity of integrated circuits has lead to the development of advanced algorithms and techniques for circuit simulation. The majority of circuit simulators rely on the Newton-Raphson algorithm for the solution of nonlinear equations that arise from the circuit description. Unfortunately, a good estimate of the root to be found is needed for the algorithm to converge. The convergence rate of the algorithm is quadratic once the method gets "close enough" to the solution, but before reaching this point the method may follow a complex route through unrealistic values of the circuit variables, leading eventually to divergence. Simulations performed with SPICE on several test circuits reveal that during the first iterations of the Newton-Raphson algorithm internal node voltages exceed the power supply voltage of several orders of magnitudes even for simple circuits. A new simulation program called MUSIC (Multilevel Simulator for Integrated Circuits) has been developed to overcome these drawbacks. In MUSIC the circuit to be simulated is decomposed in subcircuits, which may contain instances of other subcircuits up to any nesting level. Subcircuits are then simulated independently with a multilevel Newton algorithm permitting to reduce both the large oscillations that circuit variables undergo during the simulation process and the number of iterations necessary for the circuit to converge. The novel feature of this multilevel algorithm is the propagation of the already calculated terminal voltages, which become known after a subcircuit has converged, to the subcircuits connected to same terminals. In this way the information regarding node voltages is propagated through the network without constraining conditions that do not have physical counterpart. Simulations performed on chains of inverters and a 4-bit full adder evidence how MUSIC is able to improve the convergence rate and to reduce the intermediate voltage spikes.

New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 109 improvement in device lifetime is achieved.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.

Optical waveguides are one of the key devices for photonic integrated circuits considered to be one of the candidates for optical interconnects. In particular lossless bend type waveguides are necessary to integrate different optical devices monolithically. In this paper, we report on the bending loss characteristics of the multi-quantum well bend waveguide with respect to the bend radius and lateral optical mode confinement. We show that to decrease the bending loss to less than 0.5 dB, it is necessary to increase either the confinement or the bend radius. For an example, when the confinement is around 85%, the bend radius should be more than 2 mm. We also show the application of the S-bend waveguides to directional coupler type optical switch.

The crosstalk characteristics of a long-wavelength monolithically integrated photoreceiver array are analyzed. The device consists of an array of transimpedance photoreceivers fabricated on a semi-insulating InP substrate. The distance between the photodetectors is large enough to suppress the photonic crosstalk. Therefore, the crosstalk of the device is mainly due to signal propagation from the channels through the power line shared by each channel on the chip. This crosstalk is inevitable to the photoreceiver arrays which employ common power lines. The magnitude of the crosstalk largely depends on the impedance of the power-supply circuit outside the chip. The crosstalk spectrum often has a peak and recess structure. The crosstalk peak at the edge of the operating band-width is due to the resonance characteristic of the transimpedance amplifier. The other peak and recess structures on the spectrum are due to the resonance phenomena of on-chip and off-chip capacitors and inductance on the power-supply line outside the chip. This crosstalk can be reduced by using on-chip bypass capacitance and dumping resistance. However, the resonance due to the capacitance and inductance on the power-supply circuit outside the chip can't be controlled by the on-chip components. Therefore, an optimized design for the power supply circuit outside the chip is also indispensable for suppressing crosstalk.

Two types of circuit architecture for GaAs LSI are described. The first circuit is named Stacked DCFL which has supply voltage compatibility with Si CMOS/BiCMOS and ECL operating on 3 V or 3.3 V. A divide by 128/129 prescaler IC has been developed to confirm the Stacked DCFL circuit operation. The second circuit is named SVFL which operates on single supply voltage by using Schottky FET characteristics in spite of normally-on FET logic. Both circuit architectures are based on the virtual ground concept. The transition time of 45 psec was obtained by the SVFL ring oscillator circuit fabricated with 1 µm gate length FET process, and the transition time of DCFL using the same process was from 80 psec to 100 psec. Stacked DCFL and SVFL are candidates for an internal gate and an input/output interface circuit for GaAs ASIC, respectively.

Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 µm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 5125128 pixels basis screen, with a clear mode of 4.6 GByte/sec and a 4-multi column write mode of 400 MByte/sec, even using the same 0.8 µm technology as the previous VRAM (1 Mb) was realized.

To make a fast Bi-CMOS SRAM yield high without speed degradation, three defect-repair methods, the address comparison method, the fuse decoder method and the distributed fuse method, were considered in detail and their advantages and disadvantages were made clear. The distributed fuse method is demonstrated to be further improved by a built-in fuse word driver and a built-in fuse column selector, and fuse analog switches. This enhanced distributed fuse scheme was examined in a fast Bi-CMOS SRAM. A maximun access time of 14 ns and a chip size of 8.8 mm17.4 mm are expected for a 4 Mb Bi-CMOS SRAM in the future.

In this paper, a novel Y-junction type demultiplexer utilizing a stratified-waveguide configuration in the branching region is proposed for the purpose of improving the extinction ratio. A high extinction ratio of about 20 dB is achieved at 0.6328 µm and 0.83 µm operation wavelengths both for the TE and TM modes. The properties of the new type branchig waveguides which consist of the diffused waveguide and the striploaded waveguide are described to explain the operation principle. Simulation results by the BPM are also shown to check the designed values of the waveguide parameters.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

A new computer architecture using multiwavelength optoelectronic integrated circuits (OEICs) is proposed to attack the problems caused by interconnection complexity. Multiwavelength-OEIC architecures, where various wavelengths are employed as information carriers, provide the wavelength as an extra dimension of freedom for parallel processing, so that we can perform several independent computations in parallel in a single optical module using the wavelength space. This multiplex computing" enables us to reduce the wiring area required by a network and improve their complexity. In this paper, we discuss the efficient multiplexing of Batcher's bitonic sorting networks, highly parallel computing architectures that require global interconnections inherently. A systematic multiplexing of interconnection topology is presented using a binary representation of the connectivities of interconnection paths. It is shown that the wiring area can be reduced by a factor of 1/r2 using r kinds of wavelength components.

We designed and fabricated a prototype 0.4-µm-gate CMOS/SIMOX PLL LSI in order to verify the potential usefulness of ultrathin-film SIMOX technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. This PLL LSI contains both high-frequency components such a prescaler and low-frequency components such as a shift register, phase frequency comparator, and fixed divider. One application of the LSI could be for synthesizing communication band frequencies in the front-end of a battery-operated wireless handy terminal for personal communications. At a supply voltage of 2 V, this LSI operates at up to 2 GHz while dissipating only 8.4 mW. Even at only 1.2 V, 1 GHz-operation can be obtained with a power consumption of merely 1.4 mW. To explain this low-power feature, we extensively measured the electrical characteristics of individual CMOS/SIMOX basic circuits as well as transistors. Test results showed that the high performance of the LSI is mainly due to the advanced nature of the CMOS/SIMOX devices with low parasitic capacitances around source/drain regions and to the new circuit design techniques used in the dual-modulus prescalar.

We examine the characteristics of the past successful m-valued I2L and ROMs that have been designed and we discuss the reasons of their success and withdraw. We look at the problems associated with scaling of m-valued CMOS current mode circuits. Then we discuss the tolerance issue, the respective propagation delays of binary and m-valued ICs and the interconnection issue. We conclude with the challenges for m-valued circuits in the competition with the exponential performance increase of binary circuits.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.