The Single Instruction, Multiple Data (SIMD) architecture enables computation in parallel on a single processor. The SIMD operations are implemented on some processors such as Pentium 3/4, Athlon, SPARC, or even on smart cards. This paper proposes efficient algorithms for assembling an elliptic curve addition (ECADD), doubling (ECDBL), and k-iterated ECDBL (k-ECDBL) with SIMD operations. We optimize the number of auxiliary variables and the order of basic field operations used for these addition formulas. If an addition chain has k-bit zero run, we can replace k-time ECDBLs to the proposed faster k-ECDBL and the total efficiency of the scalar multiplication can be improved. Using the singed binary chain, we can compute a scalar multiplication about 10% faster than the previously fastest algorithm proposed by Aoki et al. Combined with the sliding window method or the width-w NAF window method, we also achieve about 10% faster parallelized scalar multiplication algorithms with SIMD operations. For the implementation on smart cards, we establish two fast parallelized scalar multiplication algorithms with SIMD resistant against side channel attacks.

In this paper a second order Volterra series model of an operational amplifier (opamp) circuit is presented. Such a model is suitable to the investigation of the rectification and demodulation effects of radio frequency (RF) interference superimposed on the nominal input signals and on the power supply voltage of an opamp. On the basis of the new model, some design criteria to improve the immunity of opamps to RF interference are proposed. Model predictions are verified by comparison with experimental test results.

Competition of two-photon and one-photon absorption in Si-APD was studied. Device should be cooled down in order to clearly observe two-photon absorption at low illumination intensity. Passive Geiger mode operation was studied to sensitively detect small number of carriers generated by two-photon absorption. The illumination intensity dependence of the photocurrent pulse count number is well explained by taking into account the two absorption mechanisms and a dead time period that depends on bias voltage.

The explosive increase in demand for mobile communication services has created a sudden increase in the number of subscribers to these services, and in mobile communication network traffic. Mobile communication networks contain extremely large numbers of network elements (NEs). Replacing the NE software requires extremely large numbers of provisioning workers with the advance knowledge and experience. This paper describes the basic concept of the organization hierarchy agent model, devised for application to the operation support systems (OSSs) that are being used to support provisioning works. By applying this agent model to OSSs, OSS software can be rapidly and flexibly changed to meet changes and additions to provisioning works procedures. This paper also describes the characteristics of the completed systems that apply this agent model, and presents performance evaluation results for the systems.

The design of the analog part of a mixed analog-digital IC for a commercial wireless burglar alarm system is presented as an example of a very low-power VLSI design for battery-operated systems. The main constraint is battery life, which must be at least five years (with standard camera-battery). An operational amplifier, a power supply monitor and an oscillator are the core of the design. The operational amplifier absorbs 1.5 µA while the entire analog part absorbs 4 µA. Measures on each single part show compliance with specification. Test on working environment show its full functionality. Even though the example is application specific, the design solutions and each single element can also be utilized in many other battery-operated low-frequency devices (e.g. environmental parameter monitoring).

European research Framework Programs and in particular their impact on international standardization for the development of third generation mobile communication systems are reviewed, which are currently being deployed. In 2002 the European Commission launched the 6th Framework Program. In parallel, research on systems beyond third generation started already. Therefore, international organizations such as the Wireless World Research Forum (WWRF) were established. WWRF and other international activities are presented. The vision of the Wireless World is developed from the user perspective, where already a high degree of international harmonization was achieved. The building blocks of the Wireless World and the resulting necessary major research areas are summarized. Future research projects on systems beyond third generation will focus on these topics. Global cooperation will be an important prerequisite to achieve harmonized future standards. Therefore, the 6th Framework Program of the European Commission will provide an important platform for international cooperation. The 6th Framework Program is described in detail.

The IMT-2000 service launched in 2001 in Japan is expected to popularize multimedia services such as videophone, visual mail, video, and music distribution. With the rapidly increasing demand for high-speed mobile multimedia and the need to support diversified requirements of users, wireless Quality of Service (QoS) resource management has become an important and challenging issue. In order to improve the system capacity and rate of satisfied users, in this paper, a novel wireless QoS resource management scheme is proposed to carry out radio resource cooperative control among base stations. Computer simulations indicate that the proposed QoS resource cooperative control exhibits superior performance over conventional ones, and that a higher rate of satisfied users is achieved.

Utilizing a macromodel which calculates the floating gate potential by combining resistances and dependent voltage and current sources, DC transfer characteristics for multi-input neuron MOS inverters and for those in the neuron MOS full adder circuit are simulated both at room temperature and at 77 K. Based on the simulated results, low temperature circuit failures are discussed. Furthermore, circuit design parameter optimization both for low and room temperature operations is described.

We present a new multi-stage charge pump that is suitable for low-voltage operation, and in particular for low voltage flash memory. Compare to the Dickson charge pump and previously reported modified Dickson charge pumps, the proposed charge pump offers the improved pumping voltage gains. The proposed charge pump is composed of a pair of pumps and utilizes the internal boosted voltages of one side of the paired pumps as the charge transferring voltages to the other side. The simulated and measured results indicate that the proposed pump is highly efficient in overcoming both the pumping gain decrease and the current driving capability degradation caused by the threshold voltage of the charge-transfer gate.

This paper describes an Embedded DRAM Hybrid Macro, which supports various memory specifications. The eDRAM module generator with Hybrid Macro provides more than 120,000 eDRAM configurations. This eDRAM includes a new architecture called Auto Signal Management (ASM) architecture, which automatically adjusts the timing of the control signals for various eDRAM configurations, and reduces the design Turn Around Time. An Enhanced-on-chip Tester performs the maximum 512b I/O pass/fail simultaneous judgments and the real time repair analysis. The eDRAM testing time is reduced to about 1/64 of the time required using the conventional technique. A test chip is fabricated using a 0.18 µm 4-metal embedded DRAM technology, which utilizes the triple-well, dual-Tox, and Co salicide process technologies. This chip achieves a wide voltage range operation of 1.2 V at 100 MHz to 1.8 V at 200 MHz.

A heterogeneous parallel computing environment consisting of different types of workstations and communication links plays an important role in parallel computing. In many applications on the system, collective communication operations are commonly used as communication primitives. Thus, design of the efficient collective communication operations is the key to achieve high-performance parallel computing. But the heterogeneity of the system complicates the design. In this paper, we consider design of an efficient gather operation, one of the most important collective operations. We show that an optimal gather schedule is found in O(n2k-1) time for the heterogeneous parallel computing environment with n processors of k distinct types, and that a nearly-optimal schedule is found in O(n) time if k=2.

This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 µm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

A novel linear voltage-to-current conversion circuit for a rail-to-rail input voltage is proposed in this paper. A pair of MOSFETs operating in plural regions are used for the conversion and a difference of their drain currents is used as an output current. The two MOSFETs work complemetarily and realize a rail-to-rail input range. The output current is linear in any input voltage from the ground potential to a power-supply voltage. Two types of circuit configurations which realize the proposed concept are given. From the viewpoint of area efficiency and linearity the proposed circuit is superior to a voltage-to-current converter previously proposed by the authors, which uses a set of three MOSFETs to achieve a rail-to-rail voltage-to-current conversion . The operation principle of the proposed method is confirmed through HSPICE simulations.

This paper introduces a way to realize high-pass, band-stop and all-pass transfer functions using two-integrator loop structure consisting of loss-less and lossy integrators. The basic circuit configuration is constructed with five Operational Transconductance Amplifiers (OTAs) and two grounded capacitors. It is shown that the circuit can realize their circuit transfer functions by choosing the input terminals, and that the circuit parameters can also be independently set by the transconductance gains with the proportional block. Although the basic circuit configuration has been known, it seems that the feature for realizing the high-pass, the band-stop and the all-pass transfer functions makes the structure more attractive and useful. An example is given together with simulated results by PSPICE.

A mapping circuit in order to have a wider input dynamic range is proposed. MOSFET's connecting between power supply lines are employed to construct the mapping circuit. SPICE simulation is shown to evaluate the proposed circuits. With the proposed mapping circuit, two-MOSFET subtractor has a rail-to-rail input voltage. As an application, an OTA consisting of subtractors is realized by employing the proposed mapping circuits to have a rail-to-rail input voltage range.

This paper proposes an operation-region model for analyzing and testing analog and mixed-signal circuits, which is based on observation of change in MOSFET operation regions. First, the relation between the change in MOSFET operation regions and the fault behavior of a mixed-signal circuit containing a bridging fault is investigated. Next, we propose an analysis procedure based on the operation-region model and apply it to generate the optimal input combination for testing the circuit. We also determine which transistors should be observed in order to estimate the circuit behavior. Since the operation-region model is a method for modeling circuit behavior abstractly, the proposed method will be useful for modeling circuit behavior and for analyzing and testing many kinds of analog and mixed-signal circuits.

A novel technique for automatic segmentation of a brain region in single channel MR images for visualization and analysis of a human brain is presented. The method generates a volume of brain masks by automatic thresholding using a dual curve fitting technique and by 3D morphological operations. The dual curve fitting can reduce an error in curve fitting to the histogram of MR images. The 3D morphological operations, including erosion, labeling of connected-components, max-feature operation, and dilation, are applied to the cubic volume of masks reconstructed from the thresholded brain masks. This method can automatically segment a brain region in any displayed type of sequences, including extreme slices, of SPGR, T1-, T2-, and PD-weighted MR image data sets which are not required to contain the entire brain. In the experiments, the algorithm was applied to 20 sets of MR images and showed over 0.97 of similarity index in comparison with manual drawing.

A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2 4 GB/s at 4 macros. The process cost has been kept low by using VT-MOS circuit technology and taking advantage of a characteristic of dual-gate oxide process technology. A tRAC of 11.6 ns at 2.0 V is achieved using a 'pre-detect redundancy' circuit.

Algorithms are presented for the four elementary arithmetic operations, to perform reliable floating-point arithmetic operations. These arithmetic operations can be achieved by applying residue techniques to the weighted number systems and performed with no accuracy lost in the process of the computing. The arithmetic operations presented can be used as elementary tools (on many existing architectures) to ensure the reliability of numerical computations. Simulation results especially for the solutions of ill-conditioned problems are given with emphasis on the practical usability of the tools.

This paper presents a new operation and maintenance system for PON (Passive Optical Network) subscriber loops and an assessment of its feasibility through experiments. This system adopts a broadband continuous wave light source as a testing signal and a fiber grating filter as a reflective component. The fiber grating filter is inserted somewhere in each subscriber loop for reflection of the testing signal. Our results show that the proposed system operates well for the purposes of quick decision of loop state and easy testing for PON subscriber loops.