In this study, we investigated Si(100), Si(110) and Si(111) surface flattening process utilizing sacrificial oxidation method, and its effect on Metal-Insulator-Semiconductor (MIS) diode characteristics. By the etching of the 100 nm-thick sacrificial oxide formed by thermal oxidation at 1100°C, the surface roughness of Si(100), Si(110) and Si(111) substrates were reduced. The obtained Root-Mean-Square (RMS) roughness of Si(100) was reduced from 0.22 nm (as-cleaned) to 0.07 nm (after etching), while it was reduced from 0.23 nm to 0.12 nm in the case of Si(110), and from 0.23 nm to 0.11 nm in the case of Si(111), respectively. Furthermore, it was found that time-dependent dielectric breakdown (TDDB) characteristics of MIS diodes for p-Si(100), p-Si(110) and p-Si(111) were improved with the reduction of Si surface RMS roughness.

In this study, Si(100) surface flattening process was investigated utilizing sacrificial oxidation method to improve Metal--Insulator--Semiconductor (MIS) diode characteristics. By etching of the 100,nm-thick sacrificial oxide formed by thermal oxidation at 1100$^{circ}$C, the surface roughness of Si substrate was reduced. The obtained Root-Mean-Square (RMS) roughness was decreased from 0.15,nm (as-cleaned) to 0.07,nm in the case of sacrificial oxide formed by wet oxidation, while it was 0.10,nm in the case of dry oxidation. Furthermore, time-dependent dielectric breakdown (TDDB) characteristic of Al/SiO$_{2}$(10,nm)/p-Si(100) MIS diode structures was found to be improved by the reduction of Si surface RMS roughness.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon should be realized. In this paper, flattening process of Si surface below 1000 utilizing Ar/4.9%H2 annealing and its effect on ultrathin HfON gate insulator formation were investigated. The Si(100) substrates were annealed using conventional rapid thermal annealing (RTA) system in Ar or Ar/4.9%H2 ambient for 1 h. The surface roughness of Ar/4.9%H2-annealed Si was small compared to that of Ar-annealed Si because the surface oxidation was suppressed. The obtained root mean square (RMS) roughness was 0.08 nm (as-cleaned: 0.20 nm) in case of Ar/4.9%H2-annealed at 1000 measured by tapping mode atomic force microscopy (AFM). The HfON surface was also able to be flattened by reduction of Si surface roughness. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. We obtained equivalent oxide thickness (EOT) of 0.79 nm (as-cleaned: 1.04 nm) and leakage current density of 3.510-3 A/cm2 (as-cleaned: 6.110 -1 A/cm2) by reducing the Si surface roughness.

We investigated oxidation time dependence of graphene oxide employing modified Hummer method by dynamic light scattering. Oxidation reaction proceeded rapidly within about 24 hours, and was saturated. It is suggested that graphene oxides were not able to freely fragment. This implies that the oxidation reactions occur at the limited sites.

This paper reports the DC and RF characteristics of AlN/GaN MOS-HEMTs passivated with thin Al2O3 formed by thermal oxidation of evaporated aluminium. Extraction of the small-signal equivalent circuit is also described. Device fabrication involved wet etching of evaporated Al from the Ohmic contact regions prior to metal deposition. This approach yielded an average contact resistance of ∼0.76 Ω.mm extracted from transmission line method (TLM) characterisation. Fabricated two-finger AlN/GaN MOS-HEMTs with 0.2 µm gate length and 100 µm gate width showed good gate control of drain currents up to a gate bias of 3 V and achieved a maximum drain current, IDSmax of ∼1460 mA/mm. The peak extrinsic transconductance, Gmax, of the device was ∼303 mS/mm at VDS = 4 V. Current-gain cut-off frequency, fT, and maximum oscillation frequency, fMAX, of 50 GHz and 40 GHz, respectively, were extracted from S-parameter measurements. For longer gate length, LG = 0.5 µm, fT and fMAX were 20 GHz and 30 GHz, respectively. These results demonstrate the potential of AlN/GaN MOS-HEMTs for high power and high frequency applications.

Electron cyclotron resonance (ECR) plasma oxidation of AlN thin films was studied to form the AlON high-κ gate insulator. The leakage current was found to be decreased, and also the surface roughness was improved with the ECR plasma oxidation of AlN thin films. The leakage current was further decreased after 1000 RTA in N2 with little increase of equivalent oxide thickness (EOT) because of the high quality interfacial layer formation.

We report, in this paper, on a combined process of photo-oxidation and PECVD using TEOS and O2 gases to produce an SiO2 gate insulator for poly-Si TFTs. Light of 172 nm-wavelength from a Xe excimer lamp generates active oxygen radicals efficiently and selectively without producing ozone. These oxygen radicals efficiently oxidize silicon. In contrast to plasma oxidation, photo-oxidation offers the ability to produce gate oxides without ion bombardment. Oxide-silicon interfaces with interface trap densities of 2-3 1010 cm-2 eV-1 were obtained by photo-oxidation at 200-300. A stack structure was produced using 4.3-nm-thick photo-oxide topped with a 40-nm-thick PECVD oxide film deposited at 300. This stack structure without annealing exhibited excellent interface behavior and the same J-E characteristics as a 100-nm-thick PECVD film annealed at 600.

Co-containing ferrite thin-film media deposited by a reactive-ECR-sputtering at a low substrate temperature of 150 degree Celsius were oxidized by ECR plasma. The magnetic properties and recording characteristics of the media were improved by the oxidation with maintaining a smooth surface. The media showed high D50 of 203 kFRPI in MIG head recording and reproduction. The Co-containing ferrite thin-film is feasible to be used as a protective overcoat layer.

Magnetic tunnel junctions (MTJ), i.e., structures consisting of two ferromagnetic layers (FM1 and FM2), separated by a very thin insulator barrier (I), have recently attracted attention for their large tunneling magnetoresistance (TMR) which appears when the magnetization of the ferromagnets of FM1 and FM2 changes their relative orientation from parallel to antiparallel in an applied magnetic field. Using an ultrahigh vacuum magnetron sputtering system, a variety of MTJ structures have been explored. Double Hc magnetic tunnel junction, NiFe/Al2O3/Co and FeCo/Al2O3/Co, were fabricated directly using placement of successive contact mask. The tunnel barrier was prepared by in situ plasma oxidation of thin Al layers sputter deposited. For NiFe/Al2O3/Co junctions, the maximum TMR value reaches 5.0% at room temperature, the switching field can be less than 10 Oe and the relative step width is about 30 Oe. The junction resistance changes from hundreds of ohms to hundreds of kilo-ohms and TMR values decrease monotonously with the increase of applied junction voltage bias. For FeCo/Al2O3/Co junctions, TMR values exceeding 7% were obtained at room temperature. It is surprising that an inverse TMR of 4% was observed in FeCo/Al2O3/Co. The physics governing the spin polarization of tunneling electrons remains unclear. Structures, NiFe/FeMn/NiFe/Al2O3/NiFe, in which one of the FM layers is exchange biased with an antiferromagnetic FeMn layer, were also prepared by patterning using optical lithography techniques. Thus, the junctions exhibit two well-defined magnetic states in which the FM layers are either parallel or antiparallel to one another. TMR values of 16% at room temperature were obtained. The switching field is less than 10 Oe and step width is larger than 30 Oe.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

This paper reviews the structure and electrical properties of high-quality Internal Thermal OXidation (ITOX)-processed low-dose Separation by IMplanted OXygen (SIMOX) wafers. The ITOX SIMOX process consists of three steps: low-dose oxygen implantation, high-temperature annealing, and high-temperature oxidation. The low dose makes possible a high-throughput production of SIMOX wafers. The high-temperature annealing provides a continuous buried oxide layer and reduces the dislocation density in the top silicon layer. The subsequent high-temperature oxidation thickens the buried oxide layer without any additional oxygen implantation, thus improving its electrical properties. The ITOX mechanism is also described. It is concluded that the ITOX SIMOX wafers are very useful for fabricating ULSIs.

A new observation technique for process-induced micro-defects in ULSI using a combination of anodic oxidation and chemical removal of the oxide has been developed. Enhanced oxidation has occurred at the defect region due to the stress field and then craterlike delineation has been formed after oxide removal. AFM and SEM observation of the micro-defects induced by ion implantation and applications using this tech-nique to the failure analysis of MOS device fabrication are presented.

Hydrogen termination of HF-treated Si surfaces and the oxidation kinetics have been studied by x-ray photoelectron spectroscopy (XPS) and Fourier Transform Infrared Spectroscopy (FT-IR) Attenuated Total Reflection (ATR). The oxidation of hydrogen-terminated Si in air or in pure water proceeds parallel to the surface presumably from step edges, resulting in the layer-by-layer oxidation. The oxide gryowth rate on an Si(100) surface is faster than (110) and (111) when the wafer is stored in pure water. This is interpreted in terms of the steric hindrance against molecular oxygen penetration throughth the (110) and (111) surfaces where the atom void size is equal to or smaller than O2 molecule. The oxide growth rate in pure water for heavily doped n-type Si is significantly high compared to that of heavily doped p-type Si. This is explained by the conduction electron tunneling from Si to absorbed O2 molecule to form the O2- state. O2- ions easily decompose and induce the surface electric field, enhancing the oxidation rate. It is found that the oxidation of heavily doped n-type Si in pure water is effectively suppressed by adding a small amount (1003600 ppm) of HCl.

Thermal desorption spectroscopy (TDS) is applied to analyze the oxidation reactions of hydrogen-terminated Si(100) surfaces in both the heating and cooling processes after hydrogen desorption. The oxidation reaction of oxygen and water with a silicon surface after hydrogen desorption shows hysteresis in the heating and cooling processes. In the cooling process, oxidation finishes when the silicon surface is adequately oxidized to about a 10 thickness. Oxidation continues to occur at lower temperatures when the total volume of oxygen and water is too small to saturate the bare silicon surface. The reaction of water with silicon releases hydrogen at more than 500. Hydrogen does not adsorb on the silicon oxide surface. A trace amount of oxygen, less than 110-6 Torr, roughens the surface.

The initial stages of SiO2/Si interface formation on a Si(111) surface were investigated at 300 in dry oxygen with a pressure of 133 Pa. It was found that the SiO2/Si interfacial transition layer is formed in three steps characterized by three different oxidation rates.

This paper is concerned with the stress simulation of a LOCOS structure during not only oxidation but also the subsequent cooling down based on viscoelastic stress modeling. A viscoelastic model is successfully applied to the oxide, nitride and silicon substrate for a LOCOS structure. Thermal stress is also taken into account during the cooling down process. The viscoelastic deformation problem of all the three materials for the LOCOS structure are solved by a two-dimensional finite element method. It is the first time to show that the stress values after cooling down to room temperature are much higher than those right after oxidation. It is also shown that varying the cooling down rates results in the different stress values after cooling down.

In this paper, a three part algorithm is employed to obtain stable convergence during stress dependent oxidation simulation using the finite element method is presented. By introducing (1) a reduced integration formulation, (2) an averaging procedure for the mid-side node velocities at the Si/SiO2 interface, and (3) a three-node element to discretize the oxidant diffusion equation, major improvements in achieving stable convergence are realized during stress dependent oxidation simulation. This technique is generally applicable for an oxidation simulator using the finite element method.