SiC-MOSFETs are being increasingly implemented in power electronics systems as low-loss, fast switching devices. Despite the advantages of an SiC-MOSFET, its large dv/dt or di/dt has fear of electromagnetic interference (EMI) noise. This paper proposes and demonstrates a simple and robust gate driver that can suppress ringing oscillation and surge voltage induced by the turn-off of the SiC-MOSFET body diode. The proposed gate driver utilizes the channel leakage current methodology (CLC) to enhance the damping effect by elevating the gate-source voltage (VGS) and inducing the channel leakage current in the device. The gate driver can self-adjust the timing of initiating CLC operation, which avoids an increase in switching loss. Additionally, the output voltage of the VGS elevation circuit does not need to be actively controlled in accordance with the operating conditions. Thus, the circuit topology is simple, and ringing oscillation can be easily attenuated with fixed circuit parameters regardless of operating conditions, minimizing the increase in switching loss. The effectiveness and versatility of proposed gate driver were experimentally validated for a wide range of operating conditions by double and single pulse switching tests.

We have succeeded in demonstrating high-performance four-channel 25 Gb/s integrated receiver for 100 Gb/s Ethernet with a built-in spatial Demux optics and an integrated PD array. All components which configure to the Demux optics adhered to a prism. Because of the shaping accuracy for prism, the insertion loss was able to suppress to 0.8 dB with small size. The connection point of the package for high speed electrical signals was improved to decrease the transmission loss. The small size of 12 mm 17 mm 7 mm compact package with a side-wall electrical connector has been achieved, which is compatible with the assembly in CFP2 form-factor. We observed the sensitivity at average power of -12.1 dBm and the power penalty of sensitivity due to the crosstalk of less than 0.1 dB.

A well-defined test structure of organic static-induction transistor (SIT) having regularly sized nano-apertures in the gate electrode has been fabricated by colloidal lithography using 130-nm-diameter polystyrene spheres as shadow masks during vacuum deposition. Transistor characteristics of individual nano-apertures, namely 'nano-SIT,' have been measured using a conductive atomic-force-microscope (AFM) probe as a movable source electrode. Position of the source electrode is found to be more important to increase current on/off ratio than the distance between source and gate electrodes. Experimentally obtained maximum on/off ratio was 710 (at VDS = -4 V, VGS = 0 and 2 V) when a source electrode was fixed at the edge of gate aperture. The characteristics have been then analyzed using semiconductor device simulation by employing a strongly non-linear carrier mobility model in the CuPc layer. From device simulation, source current is found to be modulated not only by a saddle point potential in the gate aperture area but also by a pinch-off effect near the source electrode. According to the obtained results, a modified structure of organic SIT and an adequate acceptor concentration is proposed. On/off ratio of the modified organic SIT is expected to be 100 times larger than that of a conventional one.

In this paper we apply a parallel adaptive solution algorithm to simulate nanoscale double-gate metal-oxide-semiconductor field effect transistors (MOSFETs) on a personal computer (PC)-based Linux cluster with the message passing interface (MPI) libraries. Based on a posteriori error estimation, the triangular mesh generation, the adaptive finite volume method, the monotone iterative method, and the parallel domain decomposition algorithm, a set of two-dimensional quantum correction hydrodynamic (HD) equations is solved numerically on our constructed cluster system. This parallel adaptive simulation methodology with 1-irregular mesh was successfully developed and applied to deep-submicron semiconductor device simulation in our recent work. A 10 nm n-type double-gate MOSFET is simulated with the developed parallel adaptive simulator. In terms of physical quantities and refined adaptive mesh, simulation results demonstrate very good accuracy and computational efficiency. Benchmark results, such as load-balancing, speedup, and parallel efficiency are achieved and exhibit excellent parallel performance. On a 16 nodes PC-based Linux cluster, the maximum difference among CPUs is less than 6%. A 12.8 times speedup and 80% parallel efficiency are simultaneously attained with respect to different simulation cases.

This paper deals with a simple and practical power loss analysis simulator, which can actually estimate the total power losses of three phase voltage-fed Auxiliary resonant commutation pole snubber assisted soft switching inverter as well as hard-switching inverter. In order to estimate the switching power losses and conduction power losses of switching semiconductor power devices (IGBTs), which are incorporated into the inverters, the proposed practical simulator is making use of feasible switching power loss data tables and conduction power loss data tables, which are accumulated from the measured voltage and current operating waveforms of power semiconductor switching devices. The practical effectiveness of feasible simulation technique and power loss evaluations for power electronic conversion circuits and systems are confirmed by the simulation and experimental results basis under the conditions of soft switching and hard switching sinusoidal PWM schemes.

This paper addresses the fundamental challenges and possible solutions in designing and fabricating nanometer-scale CMOS transistor. Essential technology components such as advanced gate dielectrics, ultra-shallow junction, channel dopant profile engineering, and salicide are discussed. Ultra-scaled transistor with physical gate length down to 15 nm is demonstrated as a continued effort to push the traditional planar CMOS technology towards its physical limit.

After a short introduction to the different requirements to and techniques for wavelength conversion, focus is on cross-gain and cross-phase modulation in SOA based converters. Aspects like jitter accumulation, regeneration and conversion to the same wavelength is discussed. It is predicted that jitter accumulation can be minimised while also assuring a high extinction ratio by using a 9-10 dB ratio between the signal and CW power. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only 20 ps of accumulated jitter and an extinction ratio of 10 dB. The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s. By controlling the input power to an EDFA, the noise redistribution and improvement of the signal-to-noise ratio is demonstrated. In a similar experiment at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of 6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced 8 dB. Obviously, the power reduction allows for longer spans between in-line EDFAs. A simple scheme for regeneration without wavelength conversion is assessed at 2.5 Gbit/s resulting in 4.5 dB lower required EDFA input power. The scheme is characterised by a quasi-digital transfer function that is ideal for regeneration. A combination of cross-gain and cross-phase conversion is used to perform conversion to the same wavelength at 20 Gbit/s. The insertion penalty for this dual-stage converter is below 2 dB and is mainly caused by extinction ratio degradation from the cross-gain converter. Finally, a new device for all-optical wavelength conversion has been proposed and 2.5 Gbit/s operation has been simulated with good results.

After a short introduction to the different requirements to and techniques for wavelength conversion, focus is on cross-gain and cross-phase modulation in SOA based converters. Aspects like jitter accumulation, regeneration and conversion to the same wavelength is discussed. It is predicted that jitter accumulation can be minimised while also assuring a high extinction ratio by using a 9-10 dB ratio between the signal and CW power. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only 20 ps of accumulated jitter and an extinction ratio of 10 dB. The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s. By controlling the input power to an EDFA, the noise redistribution and improvement of the signal-to-noise ratio is demonstrated. In a similar experiment at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of 6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced 8 dB. Obviously, the power reduction allows for longer spans between in-line EDFAs. A simple scheme for regeneration without wavelength conversion is assessed at 2.5 Gbit/s resulting in 4.5 dB lower required EDFA input power. The scheme is characterised by a quasi-digital transfer function that is ideal for regeneration. A combination of cross-gain and cross-phase conversion is used to perform conversion to the same wavelength at 20 Gbit/s. The insertion penalty for this dual-stage converter is below 2 dB and is mainly caused by extinction ratio degradation from the cross-gain converter. Finally, a new device for all-optical wavelength conversion has been proposed and 2.5 Gbit/s operation has been simulated with good results.

With the progress of LSI technology, the electronic device size is presently scaling down to the nano-meter region. In such an ultrasmall device, it is indispensable to take quantum mechanical effects into account in device modeling. In this paper, we first review the approaches to the quantum mechanical modeling of carrier transport in ultrasmall semiconductor devices. Then, we propose a novel quantum device model based upon a direct solution of the Boltzmann equation for multi-dimensional practical use. In this model, the quantum effects are represented in terms of quantum mechanically corrected potential in the classical Boltzmann equation.

The scaling laws between the design rules and the smallest sizes and numbers of particles capable of causing pattern defects and scrapping dies in semiconductor device manufacturing are described. Simulation with electromagnetic waveguide model indicates the possibility that particles, the sizes of which are of comparable order or even smaller than the wavelength of the lithography irradiation sources, are capable of causing pattern defects. For example, in the future 0.25 µm-design-rule era, the critical sizes of Si, Al, and SiO2 particles are simulated as 120 nm 120 nm, 120 nm 120 nm, and 560 nm 560 nm, respectively, in the case of 0.7 µm-thick chemically-amplified positive photoresist with 47 nm-thick top anti-reflective coating films. Future giga-scale integration era is also predicted.

We studied effects of 50-200-keV electrons on semiconductor devices using BEASTLI (backscattered electron assisting LSI inspection) method. When irradiating semiconduc-tor devices with such high-energy electrons, we have to note two phenomena. The first is surface charging and the second is device damage. In our study of surface charging, we found that a net positive charge was formed on the device surface. The positive surface charges do not cause serious influence for observation so that we can inspect wafers without problems. The positive surface charging may be brought about because most incident electrons penetrate the device layer and reach the conducting substrate of the semiconductor device. For the device damage, we studied MOS devices which were sensitive to electron-beam irradiation. By applying a 400- annealing to electron-beam irradiated MOS devices, we could restore the initial characteris-tics of MOS devices. However, in order to recover hot-carrier degradation due to neutral traps, we had to apply a 900- annealing to the electron-beam irradiated MOS devices. Thus, BEASTLI could be successfully used by providing an apporopri-ate annealing to the electron-beam irradiated MOS devices.

A new electron-beam wafer inspection system has been developed. The system has a resolution of 5 nm or better, and is applicable to quarter-micron devices such as 256 Mbit DRAMs. The most remarkable feature of this system is that a specimen stage is built in the objective lens and allows a working distance (WD) of 0. "WD=0"minimizes the effect of lens aberrations, and maximizes the resolving power. Innovative designs to achieve WD=0 are as follows: (1)A large objective lens of 730-mm width 730-mm depth 620-mm height that serves as a specimen chamber, has been developed. (2)A hollow specimen stage made of non-magnetic materials has been developed.It allows the lower pole piece and magnetic coile of the objective lens inside it. (3)Acoustic motors made of non-magnetic materials are em-ployed for use in vacuum.

This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

A new multiple-valued mask-ROM cell and a technique suitable for data detection are proposed. The information is programmed in each of the memory cells as both the threshold voltage and the channel length of the memory cell transistor, and the stored data are detected by selecting the bias condition of both the word-line and the data-line. The datum stored in the channel length is read-out using punch-through effect at the high drain voltage. The feasibility of this mask-ROM's is studied with device simulation and circuit simulation. With this design, it would be possible to get the high-density mask-ROM's, which might be faster in access speed and easier in fabrication process than the conventional ones. Therefore, this design is expected to be one of the most practical multiple-valued mask-ROM's.

A convenient method for determining emitter and base resistances from small signal measurements has been developed. This method is based on Neugroschel's method, but the frequency has been varied instead of varying β0. It is demonstrated that the base resistance was successfully extracted. The extracted emitter resistance depended on the collector current because of the difference between the exact gm value and the approximated one, IC/VT. It has also been shown that the proposed method is more robust than the conventional impedance-circle method even when cross-talk occurs.

Numerical simulation of the hydrodynamic semiconductor device equations requires powerful numerical schemes. A Space-time Galerkin/Least-Squares finite element formulation, that has been successfully applied to problems of fluid dynamic, is proposed for the solution of the hydrodynamic device equations. Similarity between the equations of fluid dynamic and semiconductor devices is discussed. The robustness and accuracy of the numerical scheme are demonstrated with the example of a single electron carrier submicron silicon MESFET device.

Narrow emitter effects in self-aligned bipolar transistors are discussed. Besides the increase of a non-ideal base current, the decrease of an ideal base current is newly observed, and a consequent fluctuation of the current gain becomes wider in the smaller emitter geometry. Both phenomena are attributed to the reduction of an emitter-impurity concentration.

This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.

This letter discusses a microstrip line with an open-end termination in which the reflected microwaves can be optically controlled by a laser illumination. The frequency characteristics are emphasized rather than the time domain ones. The reflection characteristics have been demonstrated experimentally and theoretically for the frequency range of 24 GHz. In the theoretical treatment both the conductance and the capacitance are considered in the equivalent circuit model of the open end of the strip.

Reduction in the illumination wavelength for exposure leads to higher resolution while keeping the depth of focus. Thus, KrF excimer laser lithography has been positioned as the next generation lithography tool behind g/i-line optical lithography, and many studies have been investigated. In the early days, the excimer laser lithography had many inherent problems, such as inadequate reliability, difficult maintainability, high operating cost, and low resolution and sensitivity of resist materials. However, the performance of the excimer laser stepper has been improved and chemical amplification resists have been developed for the past decade. At present, KrF excimer lithography has reached the level of trial manufacturing of lower submicron ULSI devices beyond 64 Mbit DRAMs.