The authors have developed a mechanism that applies real vibration to electrical contacts by hammering oscillation in the vertical direction similar to that in real cases, and they have studied the effects of micro-oscillation on the contacts using the mechanism. It is shown that the performance of the hammering oscillation mechanism (HOM) for measuring acceleration and force is superior to that of other methods in terms of the stability of data. Using the mechanism, much simpler and more practical protocols are proposed for evaluating acceleration, force, and mass using only the measured acceleration. It is also indicated that the relationship between the inertial force generated by the hammering oscillation mechanism and the frictional force in electrical devices attached on a board is related to one of the causes of the degradation of electrical contacts under the effect of external micro-oscillation.

Test power has become a critical issue, especially for low-power devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. However, previous capture-safety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit. This paper presents a novel metric called the Transition-Time-Relation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking. Detailed analysis done on an industrial circuit has demonstrated the advantages of the TTR metric. Capture-safety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation.

Hyperthermia is one of the modalities for cancer treatment, utilizing the difference of thermal sensitivity between tumor and normal tissue. Interstitial microwave hyperthermia is one of the heating schemes and it is applied to a localized tumor. In the treatments, heating pattern control around antennas are important, especially for the treatment in and around critical organs. This paper introduces a coaxial-dipole antenna, which is one of the thin microwave antennas and can generate a controllable heating pattern. Moreover, generations of an arbitrary shape heating patterns by an array applicator composed of four coaxial-dipole antennas are described.

Based on sample-pair refinement and local optimization, this paper proposes a high-accuracy and quick matting algorithm. First, in order to gather foreground/background samples effectively, we shoot rays in hybrid (gradient and uniform) directions. This strategy utilizes the prior knowledge to adjust the directions for effective searching. Second, we refine sample-pairs of pixels by taking into account neighbors'. Both high confidence sample-pairs and usable foreground/background components are utilized and thus more accurate and smoother matting results are achieved. Third, to reduce the computational cost of sample-pair selection in coarse matting, this paper proposes an adaptive sample clustering approach. Most redundant samples are eliminated adaptively, where the computational cost decreases significantly. Finally, we convert fine matting into a de-noising problem, which is optimized by minimizing the observation and state errors iteratively and locally. This leads to less space and time complexity compared with global optimization. Experiments demonstrate that we outperform other state-of-the-art methods in local matting both on accuracy and efficiency.

This paper proposes T-CROM (Time-delayed Collaborative ROuting and MAC) protocol, that allows collaboration between network and MAC layers in order to extend the lifetime of MANETs in a resources-limited environment. T-CROM increases the probability of preventing energy-poor nodes from joining routes by using a time delay function that is inversely proportional to the residual battery capacity of intermediate nodes, making a delay in the route request (RREQ) packets transmission. The route along which the first-arrived RREQ packet traveled has the smallest time delay, and thus the destination node identifies the route with the maximum residual battery capacity. This protocol leads to a high probability of avoiding energy-poor nodes and promotes energy-rich nodes to join routes in the route establishment phase. In addition, T-CROM controls the congestion between neighbors and reduces the energy dissipation by providing an energy-efficient backoff time by considering both the residual battery capacity of the host itself and the total number of neighbor nodes. The energy-rich node with few neighbors has a short backoff time, and the energy-poor node with many neighbors gets assigned a large backoff time. Thus, T-CROM controls the channel access priority of each node in order to prohibit the energy-poor nodes from contending with the energy-rich nodes. T-CROM fairly distributes the energy consumption of each node, and thus extends the network lifetime collaboratively. Simulation results show that T-CROM reduces the number of total collisions, extends the network lifetime, decreases the energy consumption, and increases the packet delivery ratio, compared with AOMDV with IEEE 802.11 DCF and BLAM, a battery-aware energy efficient MAC protocol.

Orthogonal arrays have important applications in statistics and computer science, as well as in coding theory. In this letter, a new construction method of symmetric orthogonal arrays of strength t is proposed, which is a concatenation of two orthogonal partitions according to a latin square. As far as we know, this is a new construction of symmetric orthogonal arrays of strength t, where t is a given integer. Based on the different latin squares, we also study the enumeration problem of orthogonal partitions, and a lower bound on the count of orthogonal partitions is derived.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, the previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes a Newton fixed-point homotopy method for MOS transistor circuits and proposes an embedding algorithm in the implementation as well. Moreover, the global convergence theorems of the proposed Newton fixed-point homotopy method for MOS transistor circuits are also proved. Numerical examples show that the efficiencies for finding DC operating points of MOS transistor circuits by the proposed MOS Newton fixed-point homotopy method with the two embedding types can be largely enhanced (can larger than 50%) comparing with the conventional MOS homotopy methods, especially for some large-scale MOS transistor circuits which can not be easily solved by the SPICE3 and HSPICE simulators.

The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.

Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.

This paper proposes a novel high-temperature superconducting dual-band bandpass filter (HTS-DBPF), that employs a broadside coupling structure, in which quarter-wavelength resonators are formed on opposite sides of each substrate. This structure provides a dual-band operation of the BPF and flexibility, in the sense of having a wide range in selecting two center passband frequencies of the HTS-DBPF. This paper employs the ratio of the lower and higher center passband frequencies, α, as a criterion for evaluating the flexibility. The obtained α ranges are from 1 to 4.7, which are the widest for DBPFs for mobile communications applications, to the best knowledge of the authors. This paper presents a 2.4-/2.9-GHz band HTS-DBPF, as an experimental example, using a YBCO film deposited on an MgO substrate. The measured frequency responses of the HTS-DBPF agree with the electromagnetic simulated results. Measurement and simulation results confirm that the proposed filter architecture is effective in configuring a DBPF that can set each center passband frequency widely.

MLPDA (Maximum Likelihood Probabilistic Data Association) has attracted a great deal of attention as an effective target track extraction method in high false density environments. However, to extract an accelerated target track on a 2-dimensional plane, the computational load of the conventional MLPDA is extremely high, since it needs to search for the most-likely position, velocity and acceleration of the target in 6-dimensional space. In this paper, we propose VG-MLPDA (Variable Gating MLPDA), which consists of the following two steps. The first step is to search the target's position and velocity among candidates with the assumed acceleration by using variable gates, which take into account both the observation noise and the difference between assumed and true acceleration. The second step is to search the most-likely position, velocity and acceleration using a maximization algorithm while reducing the gate volume. Simulation results show the validity of our method.

A coarse-grained reconfigurable architecture (CGRA) is typically hybrid architecture, which is composed of a reconfigurable processing unit (RPU) and a host microprocessor. Many computation-intensive kernels (e.g., loop nests) are often mapped onto RPUs to speed up the execution of programs. Thus, mapping optimization of loop nests is very important to improve the performance of CGRA. Processing element (PE) utilization rate, communication volume and reconfiguration cost are three crucial factors for the performance of RPUs. Loop transformations can affect these three performance influencing factors greatly, and would be of much significance when mapping loops onto RPUs. In this paper, a joint loop transformation approach for RPUs is proposed, where the PE utilization rate, communication cost and reconfiguration cost are under a joint consideration. Our approach could be integrated into compilers for CGRAs to improve the operating performance. Compared with the communication-minimal approach, experimental results show that our scheme can improve 5.8% and 13.6% of execution time on motion estimation (ME) and partial differential equation (PDE) solvers kernels, respectively. Also, run-time complexity is acceptable for the practical cases.

As mobile multimedia services expand, user behavior will become more diverse and the control of service quality from the user's perspective will become more important in service design. The quality of the network is one of the critical factors determining mobile service quality. However, this has mainly been evaluated in objective physical terms, such as delay reduction and bandwidth expansion. It is less common to use a human-centered design viewpoint when improving network performance. In this paper, we discuss ways to improve the quality of web services using time-fillers that actively address the human factors to improve the subjective quality of a mobile network. A field experiment was conducted, using a prototype. The results of the field experiment show that time-fillers can significantly decrease user dissatisfaction with waiting, but that this effect is strongly influenced by user preferences concerning content. Based on these results, we discuss the design requirements for effective use of time-fillers.

Nowadays, fault tolerance has been playing a progressively important role in covering increasing soft/hard error rates in electronic devices that accompany the advances of process technologies. Research shows that wear-out faults have a gradual onset, starting with a timing fault and then eventually leading to a permanent fault. Error detection is thus a required function to maintain execution correctness. Currently, however, many highly dependable methods to cover permanent faults are commonly over-designed by using very frequent checking, due to lack of awareness of the fault possibility in circuits used for the pending executions. In this research, to address the over-checking problem, we introduce a metric for permanent defects, as operation defective probability (ODP), to quantitatively instruct the check operations being placed only at critical positions. By using this selective checking approach, we can achieve a near-100% dependability by having about 53% less check operations, as compared to the ideal reliable method, which performs exhaustive checks to guarantee a zero-error propagation. By this means, we are able to reduce 21.7% power consumption by avoiding the non-critical checking inside the over-designed approach.

In this paper, a stochastic asymptotic stabilization method is proposed for deterministic input-affine control systems, which are randomized by including Gaussian white noises in control inputs. The sufficient condition is derived for the diffusion coefficients so that there exist stochastic control Lyapunov functions for the systems. To illustrate the usefulness of the sufficient condition, the authors propose the stochastic continuous feedback law, which makes the origin of the Brockett integrator become globally asymptotically stable in probability.

In classical routing protocols, geographical distances/locations are typically used as the metric to select the best route, under the assumption that shorter distances exhibit lower energy consumption and nodes within the communication range of the sender can receive packets with a certain success probability. However, in underwater acoustic sensor networks (UASNs), sound propagation in the ocean medium is more complex than that in the air due to many factors, including sound speed variations and the interaction of sound waves with the sea surface and floor, causing the sound rays to bend. Therefore, propagation of sound is anisotropic in water, and may cause a phenomenon called shadow zone where nodes in the communication range of the sender cannot hear any signal. This renders conventional routing protocols no longer energy-efficient. In this paper, we make use of the ray-model to account for the environment-dependent behavior of the underwater channel, re-define nodes' one-hop neighbors based on signal attenuation rather than geographical distance, and design a distributed energy-efficient routing protocol for UASNs. Results show that our ray-model-based routing policy consistently outperforms the shortest path policy, and performs very close to the optimal one in several scenarios.

A selfish routing game is a simple model of selfish behaviors in networks. It is called that Braess's paradox occurs in the selfish routing game if an equilibrium flow achieved by players' selfish behaviors is not the optimal minimum latency flow. In order to make the minimum latency flow a Nash equilibrium, a marginal cost tax has been proposed. Braess graphs have also been proposed to discuss Braess's paradox. In a large population of selfish players, conflicts between purposes of each player and the population causes social dilemmas. In game theory, to resolve the social dilemmas, a capitation tax and/or a subsidy has been introduced, and players' dynamical behaviors have been formulated by replicator dynamics. In this paper, we formulate replicator dynamics in the Braess graphs and investigate stability of the minimum latency flow with and without the marginal cost tax. An additional latency caused by the marginal cost tax is also shown. To resolve the problem of the additional latency, we extend the capitation tax and the subsidy to a state-dependent tax and apply it to the stabilization problem of the minimum latency flow.

With the technology scaling down, leakage power becomes an important part of total power consumption. The relatively large leakage current weakens the energy recovery capability of adiabatic circuits and reduces its superiority, compared with static CMOS circuits in the field of low-power design. In this paper, we rebuild three types of adiabatic circuits (2N2N2P, IPAL and DCPAL) based on FinFET devices to obtain a large leakage power reduction by rationally utilizing the different operating modes of FinFET devices (SG, LP, and IG). A 16-bit adiabatic adder has been investigated to demonstrate the advantages of FinFET adiabatic circuits. The Predictive Technology Model (PTM) is used for 32-nm bulk MOSFET and FinFET devices and all of the simulations are based on HSPICE. The results evince the proposed FinFET adiabatic circuits have a considerable reduction (more than 60% for SG mode FinFET and more than 80% for LP mode FinFET) of power consumption compared with the bulk MOSFET ones. Furthermore, the FinFET adiabatic circuits also have higher limiting frequency of clock source and better noise immunity.

We present the design of a secure identifier-based inter-domain routing, SIR, for the identifier/locator split network. On the one hand, SIR is a distributed path-vector protocol inheriting the flexibility of BGP. On the other hand, SIR separates ASes into several groups called trust groups, which assure the trust relationships among ASes by enforceable control and provides strict isolation properties to localize attacks and failures. Security analysis shows that SIR can provide control plane security that can avoid routing attacks including some smart attacks which S-BGP/soBGP can be deceived. Meanwhile, emulation experiments based on the current Internet topology with 47,000 ASes from the CAIDA database are presented, in which we compare the number of influenced ASes under attacks of subverting routing policy between SIR and S-BGP/BGP. The results show that, the number of influenced ASes decreases substantially by deploying SIR.

We propose a composite DCT basis line test signal to evaluate the video quality of a DTV encoder. The proposed composite test signal contains a frame index, a calibration square wave, and 7-field basis signals. The results show that the proposed method may be useful for an in-service video quality verifier, using an ordinary oscilloscope instead of special equipment.