This paper presents a scalable FPGA/ASIC implementation architecture for high-speed parallel table-lookup-coding using multi-ported content addressable memory, aiming at facilitating effective table-lookup-coding solutions. The multi-ported CAM adopts a Flexible Multi-ported Content Addressable Memory (FMCAM) technology, which represents an effective parallel processing architecture and was previously reported in [1]. To achieve a high-speed parallel table-lookup-coding solution, FMCAM is improved by additional schemes for a single search mode and counting value setting mode, so that it permits fast parallel table-lookup-coding operations. Evaluation results for Huffman encoding within the JPEG application show that a synthesized semi-custom ASIC implementation of the proposed architecture can already reduce the required clock-cycle number by 93% in comparison to a conventional DSP. Furthermore, the performance per area unit, measured in MOPS/mm2, can be improved by a factor of 3.8 in comparison to parallel operated DSPs. Consequently, the proposed architecture is very suitable for FPGA/ASIC implementation, and is a promising solution for small area integrated realization of real-time table-lookup-coding applications.

A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm2 and consumes 17.8 mW.

We have fabricated a polymer solid-state microstructure for optical application by two-photon-induced polymerization technique. The photopolymerization resin contains conventional laser-dye and dendrimer. A dendrimer can encapsulate the laser-dyes, limiting cluster formation and intermolecular energy transfer, and promising a high level of optical gain. The effect can be extended to prepare an optically active microstructure using the two-photon-induced polymerization technique. We fabricated a polymeric microcavity, which consisted of < 400 nm-linewidth strips arranged in layer-by-layer structure. The periodic variation in the refractive index gave rise to Bragg reflection. A laser emission was measured in the microcavity under optical excitation. The spectral linewidth was about 0.1 nm above the lasing threshold. We investigate both the material functions in the molecular scale and controlling the device structure for desired applications such as a polymer distributed feedback structure.

A micromirror for an external cavity diode laser is described. The mirror is supported by two sets of parallel torsion bars enabling piston motion as well as rotation. These motions are for realizing continuous wavelength tuning. Adjusting two rotations electrically, the pivot of the mirror rotation can be controlled. The long stroke of the vertical comb is realized by the deep three-dimensional structure prepared by the wafer bending method.

In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.41.4 mm2, and power consumption is 32 mW under a 1.8-V supply voltage.

In the design of an active matrix LCD (Liquid Crystal Display), the ratio of the pixel voltage to the video voltage (RPV) of a pixel is an important factor of the performance of the LCD, since the pixel voltage of each pixel determines its transmitted luminance. Thus, of practical importance is the issue of how to maintain the admissible allowance of RPV of each pixel within a prescribed narrow range. This constraint on RPV is analyzed in terms of circuit parameters associated with the sampling switch and sampling pulse of a column driver in the LCD. With the use of a minimal set of such circuit parameters, a design procedure is described dedicatedly for the sampling switch, which intends to seek an optimal sampling switch as well as an optimal sampling pulse waveform. A number of experimental results show that an optimal sampling switch attained by the proposed procedure yields a source driver with almost 18% less power consumption than the one by manual design. Moreover, the percentage of the RPVs within 1001% among 270 cases of fluctuations is 88.1% for the optimal sampling switch, but 46.7% for the manual design.

In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dominated by the memory modules. In deriving an optimized (for area and/or power) memory architecture, memory size computation is an important step in the exploration of the possible algorithmic specifications of multimedia applications. This paper presents a novel non-scalar approach for computing exactly the memory size in real-time multimedia algorithms. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers and, also, more recent advances in the theory of polyhedra. In contrast with all the previous works which are only estimation methods, this approach performs exact memory computations even for applications significantly large in terms of the code size, number of scalars, and number of array references.

We succeeded to fabricate p-n heterojunction and bulkheterojunction small-molecular-weight organic thin-film solar cells by combination of dry (p-type = zinc phthalocyanine, n-type = fullerene) and wet (p-type = tetra-tert-butyl zinc phthalocyanine, n-type = [6,6]-phenyl-C61-buteric acid methyl ester) processes. Relationship between morphologies of semiconducting layers and photovoltaic properties was investigated. The p-n heterojunction organic thin-film solar cells based on dry process, where surface roughness was approximately 2 nm, showed the highest power conversion efficiency of 1.3% in this paper.

A multiple-input multiple-output software defined radio (MIMO-SDR) platform was developed for implementation of MIMO transmission and propagation measurement systems. This platform consists of multiple functional boards for baseband (BB) digital signal processing and frequency conversion of 5 GHz-band radio frequency (RF) signals. The BB boards have capability of arbitrary system implementation by rewriting software on reconfigurable devices such as field programmable gate arrays (FPGAs) and digital signal processors (DSPs). The MIMO-SDR platform employs hybrid implementation architecture by taking advantages of FPGA, DSP, and CPU, where functional blocks with the needs for real-time processing are implemented on the FPGAs/DSPs, and other blocks are processed off-line on the CPU. In order to realize the hybrid implementation, driver software was developed as an application program interface (API) of the MIMO-SDR platform. In this paper, hardware architecture of the developed MIMO-SDR platform and its software implementation architecture are explained. As an application example, implementation of a real-time MIMO channel measurement system and initial measurement results are presented.

This letter proves the finish time predictability of EDZL (Earliest Deadline Zero Laxity) scheduling algorithm for multiprocessor real-time systems, which is a variant of EDF. Based on the results, it also shows that EDZL can successfully schedule any periodic task set if its total utilization is not greater than (m+1)/2, where m is the number of processors.

RBAC (Role Based Access Control) was added the concept of the role which user can have access to resources based on the role of the user, and it increased efficiency and expandability. But, evolution of computing power and internet technology has caused the up rise of the dynamic environments, in accordance with it, it will be expected to require a dynamic access control model considering various elements. In this paper, we propose DRBAC (Dynamic RBAC) model in intelligent Home (i-Home). This is an access control model suitable for user-oriented service in i-Home. In order to consider dynamic environment in the existing RBAC models, the proposed model executes assignments user-role and permission-role based on context. In addition, the proposed model provides scalable access control policies which are suitable for the characteristics of intelligent environment as considering the user location information as a temporary constraints condition. Furthermore, we design and implement WSNM (Wireless Sensor Network Module) for its services. Finally, the proposed model provides flexible and efficient authentication method which applied Domain-Group concept as well as user / device authentication.

Recently, the number of multi-homed hosts is getting large, which are equipped with multiple network interfaces to support multiple IP addresses. Although there are several proposals that aim at bandwidth aggregation for multi-homed hosts, few of them support mobility. This paper proposes a new framework called AMS: Aggregate-bandwidth Multi-homing Support. AMS provides functions of not only bandwidth aggregation but also mobility by responding to the changes of the number of connections during communication without the support of underlying infrastructure. To achieve efficient data transmission, AMS introduces a function called address pairs selection to select an optimal combination of addresses of the peer nodes. We implemented AMS in the kernel of NetBSD and evaluated it in our test network, in which dummynet was used to control bandwidth and delay. The measured results showed that AMS achieved ideal bandwidth aggregation in three TCP connections by selecting optimal address pairs.

This paper presents novel phase-continuous frequency hopping (FH) control for a direct frequency synthesizer (DFS) using a quadrature mixer driven by two direct digital synthesizers (DDSs). To achieve wideband FH in both of the lower and the upper sidebands of a local frequency in a quadrature mixer, the proposed DFS decreases or increases the phase of DDS output signals corresponding to frequency offset from a local frequency of the quadrature mixer. To realize phase decrement, the proposed method adds a complement number in a phase accumulator of a DDS, while a conventional DDS does not use phase decrement but uses a switchable combiner. In addition, as the phase accumulator output changes continuously by summing phase increment, the proposed method always assures phase continuity of a DFS output signal, which ends up suppressing sidelobe level of frequency hopped signals. The calculation and measurement results indicate that a sidelobe of a signal spectrum using the proposed phase continuous method is approximately 10 dB better than that using a conventional phase discontinuous method.

Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.

This paper describes a new low-power write driver circuit for mobile hard disk drive preamplifiers. To achieve low power consumption, we developed a write driver circuit with a single-stage MOS transistor as the current driver, which both switches and controls the write current. We also developed a reflection cancellation method to suppress the distortion of the write current waveform during write transition. Fabricated using 0.35-µm SOI-BiCMOS technology, this write driver circuit consumes low power, 380 mW (at 100 MHz).

The wave absorber which is formed by arranging cylindrical bars periodically composed of magnetic loss material and metallic bars is proposed for improving ETC environment, and characteristics of reflection loss and shielding effect are analyzed and measured. As a result, the change of various characteristics can be confirmed quantitatively by changing the thickness of magnetic loss material covering around a metallic bar and the pitch interval between bars. Furthermore, it is clarified that reflection loss of -9 dB and shielding effect of -25 dB are obtained at 5.8 GHz when the covering thickness of material is 1.5 mm and the pitch interval is 16.0 mm. Therefore, the wave absorber formed by arranging cylindrical bars that satisfies various characteristics required for the improvement of ETC environment can be realized.

We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.

This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude compared with the conventional TCAM. We also propose a novel testing methodology of the soft-error rate with a fast parallel multi-bit test. In addition, the proposed architecture resolves the critical problem of the look-up table maintenance of TCAM. The design techniques reported in this paper are especially attractive for realizing soft-error immune, high-performance TCAM chips.

A high-speed drive technique is introduced in which addressing is done by eliminating, instead of accumulating, the wall charges. In the proposed scheme, wall charges are accumulated in all the cells in advance, and then the address discharges take place in selected cells to eliminate the wall charges. Sustain discharges are generated in these cells. In order to realize the proposed address scheme, re-designing of a setup waveforms was necessary. The data pulse of 1.33 µs wide and 84 V was realized in a Ne+10%Xe PDP. A contrast of 3,600:1 was obtained by providing one setup period in a TV field.

To give comprehensive and consecutive understanding about load line regulation in the previous companion paper [1], more generalized expansion and theoretical derivation will be proposed in this paper. The paper provides an alternative current control approach to control the bias voltage compensation for full-color LED display based on the load-line approach. Modeling and formulation of the driver circuit system will be discussed in detail. Bias voltage compensation based on three load-lines regulation will keep the operating point fixed for the three color cells. Many properties can be observed based on the proposed model. Parasite effect such as the stray resistor and the stray capacitor will be considered in this paper. The associated standard RGB color testing for color cells and white color testing will be illustrated to verify the proposed compensation for the display driver circuit. The objectives of the luminance uniformity and the gray scale control can be achieved by using circuit approach. It is believed that this paper will be helpful to the driver circuit technology for the full-color LED display.