Pole-tip-driven structure, which is composed of a coil wounded at the main pole tip, is favorable for obtaining a sharp and strong head field as a single-pole-type head. Three kinds of pole-tip-driven-type heads with different yoke and coil structures are investigated in terms of magnetomotive force dependence of head field and effect of coil recession. Field calculation by finite-element method (FEM) showed that the three heads exhibited the same field sensitivity in spite of the difference in distribution of coil exciting field and magnetization of the main pole. In a lower range of magnetomotive force the heads showed different dependence of field sensitivity on the coil recession. However, there was not much difference in degradation of sensitivity in a region near the saturation of field. Thus, the importance of reducing coil recession was confirmed as reported earlier.

Multicast delivery in heterogeneous wireless networks requires careful coordination, in order to take full advantage of the resources such an interworking network environment can offer. Effective coordination, however, may require interworking signaling from coordinating network entities to receivers of a multicast service. Scalable delivery of such signaling is of great importance, since a large number of receivers may be interested in a multicast service. This paper therefore investigates the use of a multicast signaling channel (MSCH) to carry such interworking signaling in a scalable manner. Applications of interworking signaling for multicast service delivery in heterogeneous wireless networks are presented, motivating the need for an MSCH. Then a comparative study is performed analysing potential benefits of employing an MSCH for signaling message delivery compared to conventional unicast signaling. The analysis reveals that the benefits of the MSCH depend mainly on the selection of an appropriate signaling network to carry the MSCH and also on efficient addressing of a subset of receivers within the MSCH. Based on the findings, guidelines for the selection of a suitable signaling network are provided. Furthermore a novel approach is proposed that allows efficient addressing of a subset of receivers within a multicast group. The approach minimizes the required signaling load on the MSCH by reducing the size of the required addressing information. This is achieved by an aggregation of receivers with common context information. To demonstrate the concept, a prototype of the MSCH has been developed and is presented in the paper.

A quadrature demodulator (QDEMOD) for WCDMA direct-conversion receiver using a common-base input stage is reported. A common-base input stage is robust to parasitic elements and is suitable for integrating on-chip matching circuits to realize small and low-cost RF front-end modules. However, a common-mode blocker signal, such as the transmitter (TX) leakage signal, degrades the noise performance due to DC current increase and intermodulation distortion of the TX leakage signal and noise. We propose a QDEMOD with a common-base input stage capable of suppressing the TX leakage signal using symmetrical inductors. The QDEMOD was fabricated using SiGe BiCMOS process with fT of 75 GHz. The measured results show that the NF degradation does not occur until the TX leakage signal input is larger than -10 dBm.

A new quadruple watermarking scheme of digital images against geometrical attacks is proposed in this letter. We treat the center and the four vertexes of the original image as the reference points and embed the same quadruple watermarks by means of polar coordinates, which is geometrically invariant. The center of an image is assumed to not to be removed after rotating, scaling and local distortions according to the general practical image processing. In the watermark extraction process, the vertexes of the image are found by a searching method. Thus watermark synchronization is obtained. Experimental results show that the scheme is robust to the geometrical distortions including rotation, scaling, cropping and local distortions.

In this paper, a new operational amplifier is presented that improves the specifications such as dc gain, common mode rejection ratio. To obtain these improvements, we have used the two important concepts of feedback and bulk amplification.

We present the 10-bit current driver LSI with 2-set current digital-to-analog converters (DACs) and output channel current sample and hold (S/H) circuits for large-size and high-resolution active matrix organic light emitting diode (AMOLED) display applications. This current driver LSI has 300 output channels and the output current ranges from 0 µA to 290 µA. The maximum output current level can be controlled by 2-bit control signals because the maximum output current level depends on display size and resolution. The chip was fabricated using 0.65µm BiCMOS process and characterized. The chip size is 16.8 mm3.6 mm. Experimental results show that the output current DNL is less than 0.4 LSB and that INL is less than 1.5 LSB. This is good enough to apply 15.5 inch WXGA (1280RGB768) AMOLED displays.

This paper investigates fast Packet Classification techniques, where a large routing table is divided into many much smaller tables by an index key at first; the resulting small tables are much easier to search. A traditional way is to use the front bits as the index key, but we show it's not an effective way to divide a routing table. In this paper, we propose three bit selection methods for division. They can be implemented by CAM or hash structure. Simulations show that the bit selection methods decrease the delay of classification 50% compared to the traditional method. We also propose an optimized method which is adapted to the biased traffic pattern, which shows 70% improvement in our simulation.

The dry etching resistance of ArF resist patterns was improved by irradiating vacuum ultraviolet (VUV) light with a wavelength of 172 nm to ArF resist patterns in N2 atmosphere. The density of C=O bonds of the resists is decreased, and the dry etching rate of resist is also decreased after VUV irradiation. The line width shrinkage by the electron beam irradiation of CD-SEM was greatly improved from 9 nm to 2 nm, and LER (Line Edge Roughness) of resist patterns was approximately 2 nm improved from 8.4 nm to 6.5 nm under VUV irradiation. Using VUV cure, the dry etching pattern of a SiN film showed a rectangle-like cross-sectional view, and indicated almost the same LER value as the resist mask pattern. The VUV cure technique is an attractive method of fine resist pattern fabrication by ArF lithography.

For an integer d > 0, a d-queue layout of a graph consists of a total order of the vertices, and a partition of the edges into d sets of non-nested edges with respect to the vertex ordering. Recently V. Dujmovi and D. R. Wood showed that for every integer d ≥ 2, every graph G has a d-queue layout of a subdivision of G with 2logd qn(G)+1 division vertices per edge, where qn(G) is the queue number of G. This paper improves the result for the case of a bipartite graph, and shows that for every integer d ≥ 2, every bipartite graph Gm,n has a d-queue layout of a subdivision of Gm,n with logd n-1 division vertices per edge, where m and n are numbers of vertices of the partite sets of Gm,n (m ≥ n).

We propose a novel paging scheme with a variable paging interval for low power consumption and/or short paging delay. The proposed scheme is based on the fact that packet arrivals during a session follow the characteristics of self-similar process for Http service, while session arrival statistics can be modeled as the Poisson process. The adjustment of paging period provides a useful solution for efficient paging to the UE in the dormant state on packet-switched cellular networks, even though the paging performance is strongly dependent on the traffic arrival model.

We propose and experimentally demonstrate a simple method for monitoring optical signal-to-noise ratio. The novel method can be used in the optical transport networks using optical cross-connects or reconfigurable optical add-drop multiplexers. OSNR is measured by monitoring the transmitted optical power and the reflected optical power from fiber Bragg grating. We have obtained OSNR with an error less than 0.8 dB.

We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2 Mb test device has been fabricated on 130 nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1 ns row-access time is achieved and 250 MHz operation can be realized by using 2 bank 8 b-burst mode.

A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.

Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.

This letter presents a novel implementation for Bus-Invert Coding called No Invert-Line Bus-Invert Coding (NIL-BIC) architecture. It not only removes the invert-lines used in previous BIC implementations, but sends the coding information without additional bus-transitions. NIL-BIC can save about 50% more bus-power than the implementations using invert-line.

An effective way to boost power gain without noise figure degradation in a cascode low noise amplifier (LNA) is demonstrated at 4 GHz using 0.35 µm SiGe HBT technology. This approach maintains the same current consumption because a low-pass π-type LC matching network is inserted in the inter-stage of a conventional cascode LNA. 5 dB gain enhancement with no noise figure degradation at 4 GHz is observed in the SiGe HBT LNA with inter-stage matching.

A new current reused quadrature voltage controlled oscillator (QVCO) is proposed and implemented using UMC 0.18 µm CMOS 1P6M process. The proposed circuit topology is made up two low voltage LC-tank VCOs, where the QVCO is obtained using the transformer coupling and current reuse technique. At 1.8 V supply voltage, the phase noise of the VCO is -117.13 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.18 GHz, the core power consumption is 4.14 mW, the total power consumption is 6.48 mW and tuning range is about 160 MHz.

A 5.2 GHz 1 dB conversion gain, IP1 dB = -19 dBm and IIP3= -9 dBm double quadrature Gilbert downconversion mixer with polyphase filters is demonstrated by using 0.35 µm SiGe HBT technology. The image rejection ratio is better than 47 dB when LO=5.17 GHz and IF is in the range of 15 MHz to 45 MHz. The Gilbert downconverter has four-stage RC-CR IF polyphase filters for the image rejection. Polyphase filters are also used to generate LO and RF quadrature signals around 5 GHz in the double quadrature downconverter.

We report on a channel drop filter with a mode gap in the propagating mode of a photonic crystal slab that was fabricated on silicon on an insulator wafer. The results, simulated with the 3-dimensional finite-difference time-domain and plane-wave methods, demonstrated that an index-guiding mode for the line defect waveguide of a photonic crystal slab has a band gap at wave vector k = 0.5 for a mainly TM-like light-wave. The mode gap works as a distributed Bragg grating reflector that propagates the light-wave through the line defect waveguide, and can be used as an optical filter. The filter bandwidth was varied from 1-8 nm with an r/a (r: hole radius, a: lattice constant) variation around the wavelength range of 1550-1600 nm. We fabricated a Bragg reflector with a photonic crystal line-defect waveguide and Si-channel waveguides and by measuring the transmittance spectrum found that the Bragg reflector caused abrupt dips in transmittance. These experimental results are consistent with the results of the theoretical analysis described above. Utilizing the Bragg reflector, we fabricated channel dropping filters with photonic crystal slabs connected between channel waveguides and demonstrated their transmittance characteristics. They were highly drop efficient, with a flat-top drop-out spectrum at a wavelength of 1.56 µm and a drop bandwidth of 5.8 nm. Results showed that an optical add-drop multiplexer with a 2-D photonic crystal will be available for application in WDM devices for photonic networks and for LSIs in the near future.

This paper presents a novel optimized real-time Huffman encoder using a pipelined data path based on CAM technology and a parallel code-word-table optimizer. The exploitation of CAM technology enables fast parallel search of the code word table. At the same time, the code word table is optimized according to the frequency of received input symbols and is up-dated in real-time. Since these two functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. Evaluation results for the JPEG application show that the proposed architecture can achieve up to 28% smaller encoded picture sizes than the conventional architectures. The obtained encoding time can be reduced by 95% in comparison to a conventional SRAM-based architecture, which is suitable even for the latest end-user-devices requiring fast frame-rates. Furthermore, the proposed architecture provides the only encoder that can simultaneously realize small compressed data size and fast processing speed.