With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the influence on the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, a lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the "timing error risk caused by IR drop" as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new objective function. Some experimental results show the effectiveness.

An alternative polynomial expansion for electromagnetic field estimation inside three-dimensional dielectric scatterers is presented in this article. In a continuation with the previous work of authors, the Tensor-Volume Integral Equation (TVIE) is solved by using the Galerkin-based moment method (MoM) consisting of a combination of entire-domain and sub-domain basis functions including three-dimensional polynomials. Instead of using trivial power polynomials, Legendre polynomials are adopted for electromagnetic fields expansion in this study. They have the advantage of being a set of orthogonal functions, which allows the use of high-order basis functions without introducing an ill-condition MoM matrix. The accuracy of such approach in MoM is verified by comparing its numerical results with that of exact analytical method such as Mie theory and conventional procedures in MoM. Besides, it is also confirmed that the condition number of the MoM matrix obtained with the proposed approach is lower than that of the previous approaches.

It's a trend to consider the power supply integrity at early stage to improve the design quality. Specifically, floorplanning process is modified to improve the power supply as well. In the modified floorplanning process, both the floorplan and power/ground (P/G) network are adjusted to search for optimal floorplan as well as the most robust power supply. In this paper, we propose a novel algorithm to carry out this modified floorplanning. A new analytical method is proposed to estimate the voltage drop while the floorplan is varying constantly. This fast analytical voltage drop estimating method is plugged into the modified floorplanner to speed up the whole floorplanning process. Compared with previous methods, our algorithm can search for the optimal floorplan with consideration of power supply integrity more efficiently and therefore leads to better results. Furthermore, this paper also proposes a novel heuristic method to optimize the topology of P/G network. This optimization algorithm could construct a more robust power supply system. Experimental results show the method can speedup the IR-drop aware floorplanning process by about 10 times and reduce the routing area of P/G network while maintaining the floorplan quality and power supply integrity.

In this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the frame buffer and each line stores an 8 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.

The electrostatic force required for the driving of liquid droplet injected in a microchannel was studied to obtain the guiding principle to reduce the driving voltage of waveguide optical switch based on the movement of droplet. We analytically calculated the relation between the threshold voltage and velocity of droplet and the surface roughness of microchannel, and clarified some unconfirmed parameters by comparing experimental results and aeromechanical analysis. The driving of droplet in a microchannel was best analyzed using the Hagen-Poiseuille flow theory, taking into account the movement of both ends of the droplet. When the droplet is driven by some external force, a threshold of the external force occurs in the starting of movement, and hysteresis occurs in the contact angle of the droplet to the side wall of the microchannel. The hysteresis of contact angle is caused by the roughness of side wall. In our experiment, the threshold voltage ranged from 200 to 350 V and the switching time from 34 to 36 ms. The velocity of droplet was evaluated to be 0.3-0.4 mm/s from these experimental results. On the other hand, the measured angle distribution of side wall roughness ranged from 30 to 110 degrees, and the threshold voltage was evaluated to be 100-320 V, showing a good agreement with experimental results. The reduction of threshold voltage can be realized by smoothing the side wall roughness of microchannel. The switching time of 10 ms, which is required for the optical stream switch, can be obtained by shortening the horizontal spot size down to 1.5 µm.

A uniform circular array (UCA) is a well-known array configuration which can accomplish estimation of 360 field of view with identical accuracy. However, a UCA cannot estimate coherent signals because we cannot apply the SSP owing to the structure of UCA. Although a variety of studies on UCA in coherent multipath environments have been done, it is impossible to estimate the DOA of coherent signals with different incident polar angles. Then, we have proposed Root-MUSIC algorithm with a cylindrical array. However, the estimation performance is degraded when incident signals arrive with close polar angles. To solve this problem, in the letter, we propose to use SAGE algorithm with a cylindrical array. Here, we adopt a CLA Root-MUSIC for the initial estimation and decompose two-dimensional search to double one-dimensional search to reduce the calculation load. The results show that the proposal achieves high resolution with low complexity.

A novel CMOS LC quadrature oscillator (QO) which adopts complementary-coupling circuitry has been proposed. The performance improvement in I/Q phase error and phase noise of the proposed QO, is explained in comparison with conventional QOs. The proposed QO is implemented in 0.18 µm CMOS technology along with conventional QOs. The measurement result of the proposed QO shows -133.5 dBc/Hz of phase noise at 1 MHz offset and 0.6 I/Q phase difference, while oscillating at 1.77 GHz. The proposed QO shows more than 6.5 dB phase noise improvement compared to that of the conventional QOs over the offset frequency range of 10 K-1 MHz, while dissipating 4 mA from 1.4 V supply.

Because network diagrams drawn using the spring embedder are not easy to read, this paper proposes the use of "anchored maps" in which some nodes are fixed as anchors. The readability of network diagrams is discussed, anchored maps are proposed, and a method for drawing anchored maps is explained. The method uses indices to decide the orders of anchors because those orders markedly affect the readability of the network diagrams. Examples showing the effectiveness of the anchored maps are also shown.

The Letter deals with constant false alarm rate (CFAR) detection of random Gaussian target signals embedded in Gaussian clutter with unknown covariance. The proposed detector is analyzed on the assumption that clutter covariance is not known and a random target signal has low-rank property. The low-dimensional subspace-based approach leads to a robust false alarm rate (RFAR) detector. The detection performance loss and the false alarm stability loss to unknown clutter covariance have been evaluated for example scenario.

A highly integrated frequency quadrupler MMIC that uses three-dimensional MMIC (3D-MMIC) technology is presented. It consists of four driver amplifiers, two doublers, and a 2-band elimination filter. These seven circuits are integrated in only a 2.36 mm2 area. The filter sufficiently suppresses spurious output components. The third and fifth harmonic components, which are the spurious components nearest to the desired component, are well suppressed. The desired/undesired ratio is about 40 dB. The driver amplifiers make the quadrupler output a constant power of the desired multiplied signal under low input power. The MMIC supplies +5 dBm of the fourth harmonic component in the input power range from -10 dBm to +5 dBm. The power dissipation of the MMIC is only 160 mW.

Since participants at both end of the communication channel must share common pictogram interpretation to communicate, the pictogram selection task must consider both participants' pictogram interpretations. Pictogram interpretation, however, can be ambiguous. To assist the selection of pictograms more likely to be interpreted as intended, we propose a categorical semantic relevance measure which calculates how relevant a pictogram is to a given interpretation in terms of a given category. The proposed measure defines similarity measurement and probability of interpretation words using pictogram interpretations and frequencies gathered from a web survey. Moreover, the proposed measure is applied to categorized pictogram interpretations to enhance pictogram retrieval performance. Five pictogram categories used for categorizing pictogram interpretations are defined based on the five first-level classifications defined in the Concept Dictionary of the EDR Electronic Dictionary. Retrieval performances among not-categorized interpretations, categorized interpretations, and categorized and weighted interpretations using semantic relevance measure were compared, and the categorized semantic relevance approaches showed more stable performances than the not-categorized approach.

Two-dimensional resonant optical scanners actuated by vertical electrostatic combs with a unique electrical isolation structure have been developed. The isolation on the movable frame surrounding 1 mm-diameter gimbal mirror is made by trenching the top silicon layer of an SOI wafer with leaving the thick bottom layers. Thanks to the large mass of the frame, the resonant frequencies range in 65.0-89.2 Hz for the frame and in 11.9-36.8 kHz for the mirror in a 4 mm4 mm chip. The resultant frequency ratio of the fast/slow axes reaches over 500 and such a high frequency ratio is utilized to display QVGA image by raster scanning of a laser beam.

A (k,2)-track layout of a graph G consists of a 2-track assignment of G and an edge k-coloring of G with no monochromatic X-crossing. This paper studies the problem of (k,2)-track layout of bipartite graph subdivisions. Recently V. Dujmovi and D.R. Wood showed that for every integer d ≥ 2, every graph G with n vertices has a (d+1,2)-track layout of a subdivision of G with 4 log d qn(G) +3 division vertices per edge, where qn(G) is the queue number of G. This paper improves their result for the case of bipartite graphs, and shows that for every integer d ≥ 2, every bipartite graph Gm,n has a (d+1,2)-track layout of a subdivision of Gm,n with 2 log d n -1 division vertices per edge, where m and n are numbers of vertices of the partite sets of Gm,n with m ≥ n.

This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

Harmonic balance (HB) method is well known principle for analyzing periodic oscillations on nonlinear networks and systems. Because the HB method has a truncation error, approximated solutions have been guaranteed by error bounds. However, its numerical computation is very time-consuming compared with solving the HB equation. This paper proposes an algebraic representation of the error bound using Grobner base. The algebraic representation enables to decrease the computational cost of the error bound considerably. Moreover, using singular points of the algebraic representation, we can obtain accurate break points of the error bound by collisions.

This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.

A rectangular drawing is a plane drawing in which every face is a rectangle. In this paper we give a simple encoding scheme for rectangular drawings. Given a rectangular drawing R with maximum degree 3, our scheme encodes R with m + o(n) bits where n is the number of vertices of R and m is the number of edges of R. Also we give an algorithm to supports a rich set of queries, including adjacency and degree queries on the faces, in constant time.

Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gate-source and gate-drain voltages. It operates at 10 nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascode source-drain follower has the merit of small cell size. The chip was fabricated using 1.2 µm standard CMOS technology, and a wide range of operation between 1 nW and 100 µW was demonstrated. The accuracy of the voltage follower was 30 mV using minimum sized transistors, due to the variation of threshold voltage. The error in the output except for the threshold voltage mismatch was less than 10 mV. The temperature dependence of the output was 0.11 mV/. To improve the input voltage range and accuracy, non-constant biased cascode source-drain follower is examined. The sensor cell is designed for 10 mV accuracy and the cell size is 105.3µm 81.4 µm in 1.2 µm CMOS design rules. The sensor cell was fabricated and showed that the error in the output except for the threshold voltage mismatch was less than 2 mV in a range of total current between 3 nA and 10 µA and in a temperature range between 30 and 100.

A test structure to analyze asymmetry and orientation dependence of MOSFETs is presented. n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry characteristics of IDsat and IBmax with respect to the interchange of source and drain was examined. Although both IDsat and IBmax have similar channel orientation dependence, IBmax in interchanged S/D measurements shows asymmetrical characteristics, which can be applied to a sensitive method for device asymmetry detection.

In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.