In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.

A low-power high-frequency sinusoidal quadrature oscillator is presented through a new RC technique using only CMOS current mirrors. The technique is relatively simple based on (1) internal capacitances of CMOS current mirrors and (2) a resistor of a CMOS current mirror for a negative resistance. Neither external capacitances nor inductances are required. As a particular example, a 2.4 GHz-0.4 mW, 0.325-fT, CMOS sinusoidal quadrature oscillator has been demonstrated. The power consumption is very low at approximately 0.4 mW. Total harmonic distortions (THD) are less than 0.3%. The oscillation frequency is current-tunable over a range of 540 MHz or 22%. The amplitude matching and the quadrature phase matching are better than 0.035 dB and 0.15, respectively. A figure of merit called a normalized carrier-to-noise ratio (CNRnorm) is 158.79 dBc/Hz at the 2 MHz offset from 2.46 GHz. Comparisons to other approaches are also presented.

A very long instruction word (VLIW) digital signal processor (DSP), called ODiN, which could execute six instructions in a single cycle simultaneously, is designed and fabricated using 0.25 µm 1-ploy 5-metal standard cell static CMOS process. The ODiN core delivers maximum 600 MIPS with 100 MHz system clock. In order to achieve high performance operation, the designed core includes compact register files, orthogonal instruction set, single cycle operations for most instructions, and parallel processing based on software scheduling. In addition, a Viterbi decoder processor and a FFT processor that are embedded make it possible to implement software defined radio (SDR) applications efficiently.

The relation between resonant frequency of micromirror with vertical combdrives and applied voltage between the upper and lower comb teeth was analyzed. Resonant frequency of the micromirror was controlled by stiffness of the torsion hinge. Resonant frequency of the mirror was proportional to the applied voltage between the upper and lower comb teeth at the same tilt angle.

A large-swing, high-driving, low-power, class-AB buffer amplifier, which consists of a high-gain input stage and a unity-gain class-AB output stage, with low variation of quiescent current is proposed. The low power consumption and low variation of the quiescent output current are achieved by using a weak-driving and a strong-driving pseudo-source followers. The high-driving capability is mainly provided by the strong-driving pseudo-source follower whose output transistors are turned off in the vicinity of the stable state to reduce the power consumption and the variation of output current, while the quiescent state is maintained by the weak-driving pseudo-source follower. The error amplifiers with source-coupled pairs of the same type transistors are merged into a single error amplifier to reduce the area of the buffer and the current consumption. An experimental prototype buffer amplifier implemented in a 0.35-µm CMOS technology demonstrates that the circuit dissipates an average static power consumption of only 388.7 µW with the standard deviation of only 3.4 µW, which is only 0.874% at a power supply of 3.3 V, and exhibits the slew rates of 2.18 V/µs and 2.50 V/µs for the rising and falling edges, respectively, under a 300 Ω /150 pF load. Both of the second and third harmonic distortions (HD2 and HD3) are -69 dB at 20 kHz under the same load.

Let G be an undirected graph and let Γ be its drawing on a plane. Each vertex in G has a label with a specified size. In this paper, we consider the problem of placing the maximum number of vertex labels in Γ in such a way that they do not overlap any vertices, edges or other labels. By refining several portions of the Kakoulis-Tollis algorithm for labeling graphical features, we present a heuristic algorithm for this problem. Experimental results show that our algorithm can place more labels than previous algorithms.

This paper presents a new approach based on current mode circuits for fast and accurate optical level monitoring with wide dynamic range of a gigabit burst-mode laser driver chip. Our proposed solution overcomes the drawbacks that voltage mode implementations show at higher bit rates or in other technologies. The main speed-limiting factor of the level monitoring circuitry is the parasitic capacitance of the back facet monitor photodiode. We propose the use of an active-input current mirror to reduce the impact of this parasitic capacitance. The mirror produces two copies of the photo current, one to be used for the "0" level measurement and another for the "1" level measurement. The mirrored currents are compared to two reference currents by two current comparators. Every reference current needs only one calibration at room temperature. A pattern detection block scans the incoming data for patterns of sufficiently long consecutive 0's or 1's. At the end of such a pattern a valid measurement is present at the output of one of the current comparators. Based on these measurements the digital Automatic Power Control (APC) will adjust the bias (IBIAS) and modulation current (IMOD) setting of the laser driver. Tests show that the chip can stabilize and track the launched optical power with a tolerance of less than 1 dB. In these tests the pattern detection was programmed to sample the current comparators after 5 bytes (32 ns at 1.25 Gbps) of consecutive 1's and 0's. Automatic power control on such short strings of data has not been demonstrated before. Although this laser transmitter was developed for FSAN GPON applications at a speed of 1.25 Gbps upstream, the design concept is generic and can be applied for developing a wide range of burst mode laser transmitters. This chip was developed in a 0.35 µm SiGe BiCMOS process.

We propose an efficient IP address assignment protocol in mobile ad hoc networks, which use a proactive routing protocol. In this method, which is termed the Bisected-Range based Assignment (BRA), a node repeatedly broadcasts an Agent Request to ask for address assignment. If there are one or more neighbor MANET nodes, one of them becomes an agent to select and assign an IP address to the requesting node. We use address location in the IP address space so that each agent maintains its own exclusive address range to be used for address selection, resulting to decrease the possibility of address conflict. If the requesting node cannot discover any neighbor MANET node over pre-determined random agent-search time, it selects by itself an IP address at random from the given address block. We evaluate performance of the basic and enhanced BRAs by computer simulation. It is shown that the basic and enhanced BRAs can reduce address conflict compared with random assignment. It is also shown that the enhanced BRA is superior in terms of control traffic overhead as well as address assignment delay over the random assignment with the strong Duplicate Address Detection.

The transformation of a data set using a second-order polynomial mapping to find statistically independent components is considered (quadratic independent component analysis or ICA). Based on overdetermined linear ICA, an algorithm together with separability conditions are given via linearization reduction. The linearization is achieved using a higher dimensional embedding defined by the linear parametrization of the monomials, which can also be applied for higher-order polynomials. The paper finishes with simulations for artificial data and natural images.

In order to produce precise enclosures from a multi-dimensional interval vector, we introduce a sharp interval sub-dividing condition for optimization algorithms. By utilizing interval inclusion properties, we also enhance the sampling of an upper bound for effective use in the interval quadratic method. This has resulted in an improvement in the algorithm for the unconstrained optimization problem by Hansen in 1992.

The lithography process on the deep trench pattern above the large cavity is proposed to fabricate the MEMS structure. Generally, bubbles generated on the trench patterns when it was baked after coating resist. The probability of the generation of bubbles was reduced by decreasing the backing rate. The fast scanning micromirror with 50.8 kHz resonant frequency was fabricated by controlling the backing rate.

The proposed DOA (Direction Of Arrival) estimation method by integrating the frequency array data generated from microphone pairs in an equilateral-triangular microphone array is extended here. The method uses four microphones located at the apices of regular tetrahedron to enable to estimate the elevation angle from the array plane as well. Furthermore, we introduce an idea for separate estimation of azimuth and elevation to reduce the computational loads.

A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.

We have developed a novel basic technology for terahertz (THz) imaging, which allows detection and identification of chemicals by introducing the component spatial pattern analysis. The spatial distributions of the chemicals were obtained from terahertz multispectral transillumination images, using absorption spectra previously measured with a widely tunable THz-wave parametric oscillator. We have also separated the component spatial patterns of frequency-dependent absorptions in chemicals and frequency-independent components such as plastic, paper and measurement noise in THz spectroscopic images. Further we have applied this technique to the detection and identification of illicit drugs concealed in envelopes.

This letter proposes an output driver which reduces simultaneous switching noise without degradation of rise/fall time. At the start of transition period, the driver optimally uses both VDD and VSS current by switching of on-chip bypass capacitors. The proposed driver achieves 27-percent reduction in peak current with faster transition time.

An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operation is achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.

Dynamic non-linearities are of more importance in highly-linear high-speed applications such as software radios. In this paper, a fully-analytical approach to estimate the statistics of dynamic non-linearity parameters of pipeline analog-to-digital converters (ADCs) in the presence of circuit non-idealities is presented. These imperfections include the capacitor mismatches and the non-idealities in the operational amplifiers (op-amps). The most two important ADC dynamic non-linearity parameters, the spurious-free dynamic range (SFDR) and the signal-to-noise-and-distortion ratio (SNDR) are quantified here and closed-form formulas are presented. These formulas are useful for design automation as well as hand calculations of highly-linear pipeline ADCs. Behavioral simulations are presented to show the accuracy of the proposed equations.

We propose a new method to recover scene points from a single calibrated view using a subset of distances among the points. This paper first introduces the problem and its relationship with the perspective n point problem. Then the number of distances required to uniquely recover scene points are explored. The result is then developed into a practical vision algorithm to calculate the initial points' coordinates using distance constraints. Finally SQP (Sequential Quadratic Programming) is used to optimize the initial estimations. It can minimize a cost function defined as the sum of squared reprojection errors while keeping the specified distance constraints strictly satisfied. Both simulation data and real scene images have been used to test the proposed method, and good results have been obtained.

A rigorous analysis for a TM010 mode cylindrical cavity with insertion holes is presented on the basis of the Ritz-Galerkin method to realize accurate measurements of the complex permittivity of liquid. The effects of sample insertion holes, a dielectric tube, and air-gaps between a dielectric tube and sample insertion holes are taken into account in this analysis. The validity of this method is verified from measured results of some kinds of liquid.

A K-band monolithic driver amplifier with equalizer circuits has been developed. It is necessary for the equalizer circuit to be low losses in the high-frequency range and for its S21 values to increase as the operation frequency increases. In order to realize these features, it is desirable for the equalizer to have element location considering high-frequency current flows. In this paper, we present a novel low-loss, high-pass equalizer circuit layout that has superior characteristics in the high-frequency range. We used a high-pass filter as the equalizer circuit and performed a detailed evaluation of the high-frequency characteristics of the filter circuit test element groups (TEGs) for three layout types. It was found that the best filter circuit layout for the three types consisted of two capacitors and one resistor, placed with parallel connections. The resistor is located at the center and the capacitors are located at both sides of the resistor. This filter is called the CRC-type in this paper. An MMIC test sample, a K-band monolithic amplifier with CRC-type filter circuits, was fabricated. The amplifier had a gain of 21.6 dB, a Rollett stability factor K of 28.9, an input VSWR of 1.63, an output VSWR of 1.92, and a 1 dB compressed output power of 22.6 dBm at 26 GHz.