A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm2 and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.

The concepts of M-convexity and L-convexity, introduced by Murota (1996, 1998) for functions on the integer lattice, extract combinatorial structures in well-solved nonlinear combinatorial optimization problems. These concepts are extended to polyhedral convex functions and quadratic functions on the real space by Murota-Shioura (2000, 2001). In this paper, we consider a further extension to general convex functions. The main aim of this paper is to provide rigorous proofs for fundamental properties of general M-convex and L-convex functions.

We presented a wall charge controlled ac PDP driving method which has advantages of less number of sub-fields and no dynamic false contours compared to the conventional driving method. In this method, a sub-field exhibited different light intensity according to the initial wall charge quantity set during the address period. Even though one can set 10 different wall charge states by changing the data pulse widths, we decided to define three states, 'on,' 'half-on,' and 'off.' By adding one state, the number of sub-field required to achieve 243 gray levels was reduced from 8 to 5. Furthermore, one can realize seven sub-fields, 255 gray level, complete stretched-out coding with which one can eliminate the dynamic false contours. Since this method can reduce number of sub-fields, it is suitable for higher resolution PDP's with more scan lines.

In this paper, we propose a simple and accurate transfer function model of the power amplifiers for mobile communications. Detail analysis yields a generalized model for AM/AM characteristics in classes AB, B, and C. The analysis includes the effect of drain current variation with input level variation. This model introduces a loadline variation ratio to indicate the change of drain current and to represent the operation classes in a small signal region. Further discussion leads to simplified approximate equations for the AM/AM characteristics, and the estimation procedures for the simplified model parameters. Using the derived procedures, an efficient power amplifier employing pseudomorphic high electron mobility transistor (PHEMT) is fabricated for the 2 GHz band. Finally, the various characteristics given by the model, simulator and measurements are compared and found to agree well in the range of 20 dB below the saturated output level. The model is very effective for characterizing the power amplifiers that are used in linear compensation techniques such as predistortion methods, due to its severe nonlinearity of AM/AM and AM/PM characteristics.

This paper proposes a sensing and a precharge circuit schemes suitable for low-voltage and high-speed DRAM design. The proposed offset-compensated direct sensing scheme improves refresh characteristics as well as speed performance. To minimize the number of control switches for the offset compensation, only the output branches of differential amplifiers are implemented in each bit-line pair with a semi-global bias branch, which also reduces 50-percent of bias current. The addition of the direct sensing feature to the offset-compensated pre-sensing dramatically increases the differential current output. For the fast bit-line equalization, a charge-recycled precharge scheme is proposed to reuse VPP discharging current for the generation of a boosted bias without additional charge pumping. The two circuit schemes were verified by the implementation of a 256 Mb SDRAM with a 0.1 µm dual-doped poly-silicon technology.

Satellite communication can be operated with various levels of on-board processing in order to transmit the signal effectively. In this paper, the BER performances of the bent pipe transponder (BPT), dehop only transponder (DOT) and dehop and rehop transponder (DRT) systems with FH-MFSK modulation are investigated in the presence of broad band interference, narrow band interference and tone-type interference. In this case, the BER performances are compared for the variants of the data rates, spreading bandwidth and interference power. The numerical results show that DRT outperforms BPT and DOT. DOT is less sensitive to uplink interference power under broad band interference environment than DRT. In the case of narrow band interference, the DRT system is more sensitive to ρ value, i.e., the ratio of the interference bandwidth to the spreading bandwidth, than DOT. Among various interference types, the performance in n = 1 band multi-tone interference is shown to be the worst.

A 2-dimensional cylindrical k-within-consecutive-(r, s)-out-of-(m, n):F system consists of m n components arranged on a cylindrical grid. Each of m circles has n components, and this system fails if and only if there exists a grid of size r s within which at least k components are failed. This system may be used into reliability models of "Feelers for measuring temperature on reaction chamber," "TFT Liquid Crystal Display system with 360 degree wide area" and others. In this paper, first, we propose an efficient algorithm for the reliability of a 2-dimensional cylindrical k-within-consecutive-(r, s)-out-of-(m, n):F system. The feature of this algorithm is calculating their system reliabilities with shorter computing time and smaller memory size than Akiba and Yamamoto. Next, we show some numerical examples so that our proposed algorithm is more effective than Akiba and Yamamoto for systems with large n.

In this paper we propose a new blind adaptive compensator associated with the inverse QRD-RLS (IQRD-RLS) algorithm to adaptively estimate the parameters, related to the effects of gain/phase imbalance and DC offsets occur in the Quadrature demodulator, for compensation. In this new approach the power measurement of the received signal is employed to develop the blind adaptation algorithm for compensator, it does not require any reference signal transmitted from the transmitter and possess the fast convergence rate and better numerical stability. To verify the great improvement, in terms of reducing the effects of the imbalance and offset, over existing techniques computer simulation is carried out for the coherent 16 PSK-communication system. We show that the proposed blind scheme has rapidly convergence rate and the smaller mean square error in steady state.

We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.

This paper describes low voltage write driver with pulse adding circuit. The presented write driver is constructed from the main switch circuit with impedance matching and pulse adding circuits and a timing generator. The main switch circuit is voltage type driver with matching resisters for flexible lines between a write driver and a write head. For 1.2 Gbps operation, the flexible lines have to be treated as transmission lines. Furthermore, to achieve steep rise/fall edge, the pulse adding circuits to generate double of supply voltage, +3.3/-3 V, at rise/fall edge have been developed. The write driver was implemented using 0.35 µm BiCMOS process. The die size is 1.2 mm0.6 mm and the measured results achieved tr/tf of less than 0.25 ns, tp of 0.5 ns and Ip of 73 mA.

We developed a compact, 16-channel integrated optical subscriber module for one-fiber bi-directional optical access systems. They can support more subscribers in a limited mounting space. For ultimate compactness, we created 8-channel integrated super-compact optical modules, 4-channel integrated limiting amplifiers, and 4-channel integrated LD drivers for Fast Ethernet. We introduce a new simulation method to analyze the electrical crosstalk that degrades sensitivity of the optical module. A new IC architecture is applied to reduce electrical crosstalk. We manufactured the optical subscriber module with these optical modules and ICs. Experiments confirm that the module offers a sensitivity of -27.3 dBm under 16-channel 125 Mbit/s simultaneous operation.

Most of system-on-chips (SOCs) have many memory cores. Diagnosis is often used to improve the yield of memories. Memory cores usually represent a significant portion of the chip area and dominate the yield of the chip. Memory diagnosis thus is one of key techniques for improving the yield and quality of SOCs. Content addressable memories (CAMs) are important components in many SOCs. In this paper we propose a three-phase diagnosis procedure for binary CAMs (BCAMs). The user can distinguish different types of BCAM-specific comparison and RAM faults and locate the faulty cells with the procedure. A March-like fault identification algorithm is also proposed. The algorithm can distinguish different types of faults--including typical RAM faults and BCAM-specific comparison faults. The algorithm requires 15N Read/Write operations and 2(N + B) Compare operations for an N B-bit BCAM. Analysis results show that the algorithm has 100% diagnostic resolution for the target faults.

As semiconductor manufacturing technology advances, power dissipation and noise in scan testing have become critical problems. Our studies on practical LSI manufacturing show that power supply voltage drop causes testing problems during shift operations in scan testing. In this paper, we present a new testing method named MD-SCAN (Multi-Duty SCAN) which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.

In this paper, we focus on how to correct address mapping violation, in which an attacker rewrites the address mapping table of a victim to perform a Man-in-the-Middle (MITM) attack. We propose a technique for preventing MITM attacks in which a malicious user intercepts and possibly alters the data transmitted between two hosts. MITM attack is hard for legitimate users to notice during their normal communication, because each user believes they are communicating directly. Address mapping violation can occur because of vulnerability of address resolution protocols, Address Resolution Protocol (ARP) in IPv4 and Neighbor Discovery (ND) protocol in IPv6. Accordingly, a good method to prevent MITM attack by address mapping violation is essential for both current and future communications, i.e. wireless networks with roaming users and an interconnected world. Hence, our proposal mainly aims to have high usability in future applications such as embedded devices.

A novel multi-phase charge-sharing technique is proposed for the dot-inversion method to reduce AC power consumption of the TFT-LCD column driver without requiring any external capacitor for charge conservation. Simple and easy-to-control circuitry is applied in the proposed method, and the power saving efficiency depends on number of charge phases. Increasing the number of charge phases, the saving power efficiency is also raised. Excluding power dissipation of switches, the power saving efficiency is up to 75% theoretically with infinite phases. For previous work, the maximum power saving efficient is 50% without external capacitor. The HSPICE simulation results including power dissipation of all switches show that the proposed method with seven charge phases (eight-column lines as one group) decreases the power consumption of 23-68% and 10-18%, respectively, compared with original circuit (without any low-power scheme) and previous low-power charge-recycling works.

Graph drawing addresses the problem of constructing geometric representation of information and finds applications in almost every branch of science and technology. Efficient algorithms are essential for automatic drawings of graphs, and hence a lot of research has been carried out in the last decade by many researchers over the world to develop efficient algorithms for drawing graphs. In this paper we survey the recent algorithmic results on various drawings of plane graphs: straight line drawing, convex drawing, orthogonal drawing, rectangular drawing and box-rectangular drawing.

This paper describes a novel method of shape matching by means of unification and expansion of local correspondences on the feature points. The method has the ability to simultaneously locate plural similar parts of two-dimensional objects under affine transformation. Furthermore, the method is applicable to the objects partially occluded. Experimental results show that the method yields results that are satisfactory, even for the cases with additions, deletions and local deviations of some feature points.

Temperature dependence of drain current is analyzed in detail in terms of mobility and threshold voltage. From the analyses, it is proved that a point exists that the drain current is fixed without depending on temperature when the MOSFET operates in strong inversion. Applying this characteristic, a CMOS temperature-voltage converter operating in strong inversion with high linearity is proposed. SPICE simulation and experimental results are shown, and the corresponding performances are discussed.

This paper describes feasibility of a proposed fixed wireless access system with CDMA technology. The system adopts a primary modulation of 16 QAM and the same frequency allocation in all cells to improve spectral efficiency. The system capacity is 1 Gbps per cell within 120 MHz bandwidth. The number of available orthogonal codes corresponds to the orthogonal code length in the system. All subscribers can attain an error free condition with output power control in the presence of inter-cell interference. The following two items are considered to examine the proposed system feasibility. 1) A test modem is fabricated, and a back-to-back modem BER performance is measured. An inter-symbol interference (ISI) level of the modem is estimated with the measured performance. 2) A computer simulation of down-link power control is carried out considering inter-cell interference and impairment factors of the power control such as intra-sector interference caused by the ISI and limited ranges of total and relative output power controls. The simulation results show that the proposed system would be feasible because the obtained power penalties caused by the above impairment factors are negligible.

In this paper, using the exact expression for the pairwise error probability derived in terms of the message symbol distance between two message vectors rather than the codeword symbol distance between two transmitted codeword matrices, the exact closed form expressions for the symbol error probability of any linear orthogonal space-time block codes in slow Rayleigh fading channel are derived for QPSK, 16-QAM, 64-QAM, and 2 56-QAM.