Reservoir computing (RC) is an attractive alternative to machine learning models owing to its computationally inexpensive training process and simplicity. In this work, we propose EnsembleBloomCA, which utilizes cellular automata (CA) and an ensemble Bloom filter to organize an RC system. In contrast to most existing RC systems, EnsembleBloomCA eliminates all floating-point calculation and integer multiplication. EnsembleBloomCA adopts CA as the reservoir in the RC system because it can be implemented using only binary operations and is thus energy efficient. The rich pattern dynamics created by CA can map the original input into a high-dimensional space and provide more features for the classifier. Utilizing an ensemble Bloom filter as the classifier, the features provided by the reservoir can be effectively memorized. Our experiment revealed that applying the ensemble mechanism to the Bloom filter resulted in a significant reduction in memory cost during the inference phase. In comparison with Bloom WiSARD, one of the state-of-the-art reference work, the EnsembleBloomCA model achieves a 43× reduction in memory cost while maintaining the same accuracy. Our hardware implementation also demonstrated that EnsembleBloomCA achieved over 23× and 8.5× reductions in area and power, respectively.

Currently, wireless power transmission technology is being developed for capsule endoscopes. By removing the battery, the capsule endoscope is miniaturized, the number of images that can be taken increases, and the risk of harmful substances leaking from the battery when it is damaged inside the body is avoided. Furthermore, diagnostic accuracy is improved by adjusting the directivity of radio waves according to the position of the capsule endoscope to improve efficiency and adjusting the number of images to be taken according to position by real-time position estimation. In this study, we report the result of position estimation in a high-definition numerical human body model and in an experiment on an electromagnetic phantom.

The resistor variation can severely affect current reference sources, which may vary up to ±40% in scaled CMOS processes. In addition, such variations make the opamp design challenging and increase the design margin, impacting power consumption. This paper proposes a Time-Based Current Source (TBCS): a robust and process-scalable reference current source suitable for switched-capacitor (SC) circuits. We construct a delay-locked-loop (DLL) to lock the current-starved inverter with the reference clock, enabling the use of the settled current directly as a reference current. Since the load capacitors determine the delay, the generated current is decoupled from resistor values and enables a robust reference current source. The prototype TBCS fabricated in 28nm CMOS achieved a minimal area of 1200um2. The current variation is suppressed to half compared to BGR based current sources, confirmed in extensive PVT variation simulations. Moreover, when used as the opamp's bias, TBCS achieves comparable opamp GBW to an ideal current source.

Recently, with the spread of Internet of Things (IoT) devices, embedded hardware devices have been used in a variety of everyday electrical items. Due to the increased demand for embedded hardware devices, some of the IC design and manufacturing steps have been outsourced to third-party vendors. Since malicious third-party vendors may insert malicious circuits, called hardware Trojans, into their products, developing an effective hardware-Trojan detection method is strongly required. In this paper, we propose 25 hardware-Trojan features focusing on the structure of trigger circuits for machine-learning-based hardware-Trojan detection. Combining the proposed features into 11 existing hardware-Trojan features, we totally utilize 36 hardware-Trojan features for classification. Then we classify the nets in an unknown netlist into a set of normal nets and Trojan nets based on a random-forest classifier. The experimental results demonstrate that the average true positive rate (TPR) becomes 64.2% and the average true negative rate (TNR) becomes 100.0%. They improve the average TPR by 14.8 points while keeping the average TNR compared to existing state-of-the-art methods. In particular, the proposed method successfully finds out Trojan nets in several benchmark circuits, which are not found by the existing method.

As known to us all, L-shaped co-prime array (LCA) is a recently introduced two-dimensional (2-D) sparse array structure, which is extended from linear co-prime array (CA). Such sparse array geometry can be used for 2-D parameters estimation with higher degrees-of-freedom (DOF). However, in the scenario where several narrowband transmissions spread over a wide spectrum, existing technique based on LCA with Nyquist sampling may encounter a bottleneck for both analog and digital processing. To alleviate the burden of high-rate Nyquist sampling, a method of joint wideband spectrum and direction-of-arrival (DOA) estimation with compressed sampling based on LCA, which is recognized as LCA-based modulated wideband converter (MWC), is presented in this work. First, the received signal along each antenna is mixed to basebands, low-pass filtered and down-sampled to get the compressed sampling data. Then by constructing the virtual received data of 2-D difference coarray, we estimate the wideband spectrum and DOA jointly using two recovery methods where the first is a joint ESPRIT method and the other is a joint CS method. Numerical simulations illustrate the validity of the proposed LCA based MWC system and show the superiority.

This paper proposes two accurate source-number estimation methods for array antennas and multi-input multi-output radar. Direction of arrival (DOA) estimation is important in high-speed wireless communication and radar imaging. Most representative DOA estimation methods require the source-number information in advance and often fail to estimate DOAs in severe environments such as those having low signal-to-noise ratio or large transmission-power difference. Received signals are often bandlimited or narrowband signals, so the proposed methods first involves denoising preprocessing by removing undesired components then comparing the original and denoised signal information. The performances of the proposed methods were evaluated through computer simulations.

A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic device. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, and several low-latency AQFP logic gates have been demonstrated. In delay-line clocking, the latency between adjacent excitation phases is determined by the propagation delay of excitation currents, and thus the rising time of excitation currents should be sufficiently small; otherwise, an AQFP gate can switch before the previous gate is fully excited. This means that delay-line clocking needs high clock frequencies, because typical excitation currents are sinusoidal and the rising time depends on the frequency. However, AQFP circuits need to be tested in a wide frequency range experimentally. Hence, in the present study, we investigate AQFP circuits adopting delay-line clocking with square excitation currents to apply delay-line clocking in a low frequency range. Square excitation currents have shorter rising time than sinusoidal excitation currents and thus enable low frequency operation. We demonstrate an AQFP buffer chain with delay-line clocking using square excitation currents, in which the latency is approximately 20ps per gate, and confirm that the operating margin for the buffer chain is kept sufficiently wide at clock frequencies below 1GHz, whereas in the sinusoidal case the operating margin shrinks below 500MHz. These results indicate that AQFP circuits adopting delay-line clocking can operate in a low frequency range by using square excitation currents.

We experimentally evaluated random number sequences generated by a superconducting hardware random number generator composed of a Josephson-junction oscillator, a rapid-single-flux-quantum (RSFQ) toggle flip-flop (TFF), and an RSFQ AND gate. Test circuits were fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. Measurements were conducted in a liquid helium bath. The random numbers were generated for a trigger frequency of 500 kHz under the oscillating Josephson-junction at 29 GHz. 26 random number sequences of 20 kb length were evaluated for bias voltages between 2.0 and 2.7 mV. The NIST FIPS PUBS 140-2 tests were used for the evaluation. 100% pass rates were confirmed at the bias voltages of 2.5 and 2.6 mV. We found that the Monobit test limited the pass rates. As numerical simulations suggested, a detailed evaluation for the probability of obtaining “1” demonstrated the monotonical dependence on the bias voltage.

As the basis of fine breeding management and animal husbandry insurance, individual recognition of dairy cattle is an important issue in the animal husbandry management field. Due to the limitations of the traditional method of cow identification, such as being easy to drop and falsify, it can no longer meet the needs of modern intelligent pasture management. In recent years, with the rise of computer vision technology, deep learning has developed rapidly in the field of face recognition. The recognition accuracy has surpassed the level of human face recognition and has been widely used in the production environment. However, research on the facial recognition of large livestock, such as dairy cattle, needs to be developed and improved. According to the idea of a residual network, an improved convolutional neural network (Res_5_2Net) method for individual dairy cow recognition is proposed based on dairy cow facial images in this letter. The recognition accuracy on our self-built cow face database (3012 training sets, 1536 test sets) can reach 94.53%. The experimental results show that the efficiency of identification of dairy cows is effectively improved.

Extremely energy-efficient logic devices are required for future low-power high-performance computing systems. Superconductor electronic technology has a number of energy-efficient logic families. Among them is the adiabatic quantum-flux-parametron (AQFP) logic family, which adiabatically switches the quantum-flux-parametron (QFP) circuit when it is excited by an AC power-clock. When compared to state-of-the-art CMOS technology, AQFP logic circuits have the advantage of relatively fast clock rates (5 GHz to 10 GHz) and 5 - 6 orders of magnitude reduction in energy before cooling overhead. We have been developing extremely energy-efficient computing processor components using the AQFP. The adder is the most basic computational unit and is important in the development of a processor. In this work, we designed and measured a 16-bit parallel prefix carry look-ahead Kogge-Stone adder (KSA). We fabricated the circuit using the AIST 10 kA/cm2 High-speed STandard Process (HSTP). Due to a malfunction in the measurement system, we were not able to confirm the complete operation of the circuit at the low frequency of 100 kHz in liquid He, but we confirmed that the outputs that we did observe are correct for two types of tests: (1) critical tests and (2) 110 random input tests in total. The operation margin of the circuit is wide, and we did not observe any calculation errors during measurement.

With the increasing densification of 5G and future 6G networks high-capacity backhaul links to connect the numerous base stations become an issue. Since not all base stations can be connected via fibre links for either technical or economic reasons wireless connections at 300GHz, which may provide data rates comparable to fibre links, are an alternative. This paper deals with the planning of 300GHz backhaul links and describes two novel automatic planning approaches for backhaul links arranged in ring and star topology. The two planning approaches are applied to various scenarios and the corresponding planning results are evaluated by comparing signal to interference plus noise ratio under various simulation conditions including weather impacts showing the feasibility of wireless backhaul links.

Quantum combinatorial designs are gaining popularity in quantum information theory. Quantum Latin squares can be used to construct mutually unbiased maximally entangled bases and unitary error bases. Here we present a general method for constructing quantum Latin arrangements from irredundant orthogonal arrays. As an application of the method, many new quantum Latin arrangements are obtained. We also find a sufficient condition such that the improved quantum orthogonal arrays [10] are equivalent to quantum Latin arrangements. We further prove that an improved quantum orthogonal array can produce a quantum uniform state.

In this paper, we review the basic components of superconducting quantum computers. We mainly focus on the packaging and wiring technologies required to realize large-scalable superconducting quantum computers.

Pairing computations on elliptic curves with odd prime degrees are rarely studied as low efficiency. Recently, Clarisse, Duquesne and Sanders proposed two new curves with odd prime embedding degrees: BW13-P310 and BW19-P286, which are suitable for some special cryptographic schemes. In this paper, we propose efficient methods to compute the optimal ate pairing on this types of curves, instantiated by the BW13-P310 curve. We first extend the technique of lazy reduction into the finite field arithmetic. Then, we present a new method to execute Miller's algorithm. Compared with the standard Miller iteration formulas, the new ones provide a more efficient software implementation of pairing computations. At last, we also give a fast formula to perform the final exponentiation. Our implementation results indicate that it can be computed efficiently, while it is slower than that over the (BLS12-P446) curve at the same security level.

A variety of smart services are being provided on multiple virtual networks embedded into a common inter-cloud substrate network. The substrate network operator deploys critical substrate nodes so that multiple service providers can achieve enhanced services due to the secure sharing of their service data. Even if one of the critical substrate nodes incurs damage, resiliency of the enhanced services can be assured due to reallocation of the workload and periodic backup of the service data to the other normal critical substrate nodes. However, the connectivity of the embedded virtual networks must be maintained so that the enhanced services can be continuously provided to all clients on the virtual networks. This paper considers resilient virtual network embedding (VNE) that ensures the connectivity of the embedded virtual networks after critical substrate node failures have occurred. The resilient VNE problem is formulated using an integer linear programming model and a distance-based method is proposed to solve the large-scale resilient VNE problem efficiently. Simulation results demonstrate that the distance-based method can derive a sub-optimum VNE solution with a small computational effort. The method derived a VNE solution with an approximation ratio of less than 1.2 within ten seconds in all the simulation experiments.

Goal refinement is a crucial step in goal-oriented requirements analysis to create a goal model of high quality. Poor goal refinement leads to missing requirements and eliciting incorrect requirements as well as less comprehensiveness of produced goal models. This paper proposes a technique to automate detecting bad smells of goal refinement, symptoms of poor goal refinement. At first, to clarify bad smells, we asked subjects to discover poor goal refinement concretely. Based on the classification of the specified poor refinement, we defined four types of bad smells of goal refinement: Low Semantic Relation, Many Siblings, Few Siblings, and Coarse Grained Leaf, and developed two types of measures to detect them: measures on the graph structure of a goal model and semantic similarity of goal descriptions. We have implemented a supporting tool to detect bad smells and assessed its usefulness by an experiment.

In this letter, the almost binary sequence (sequence with a single zero element) is considered as a special class of binary sequence. Four new bounds on the cross-correlation of balanced (almost) binary sequences with period Q ≡ 1(mod 4) under the precondition of out-of-phase autocorrelation values {-1} or {1, -3} are firstly presented. Then, seven new pairs of balanced (almost) binary sequences of period Q with ideal or optimal autocorrelation values and meeting the lower cross-correlation bounds are proposed by using cyclotomic classes of order 4. These new bounds of (almost) binary sequences with period Q achieve smaller maximum out-of-phase autocorrelation values and cross-correlation values.

This paper presents a design method of a two-hop wireless power transfer (WPT) system for installing on a robot arm. The class-E inverter and the class-D rectifier are used on the transmission and receiving sides, respectively, in the proposed WPT system. Analytical equations for the proposed WPT system are derived as functions of the geometrical and physical parameters of the coils, such as the outer diameter and height of the coils, winding-wire diameter, and number of turns. Using the analytical equations, we can optimize the WPT system to obtain the design values with the theoretically highest power-delivery efficiency under the size limitation of the robot arm. The circuit experiments are in quantitative agreement with the theoretical predictions obtained from the analysis, indicating the validity of the analysis and design method. The experimental prototype achieved 83.6% power-delivery efficiency at 6.78MHz operating frequency and 39.3W output power.