Geomagnetic information is informative because it has the ability to detect information about orientation by way of a ubiquitous device. However, a magnetic disturbance easily influences geomagnetic information. The magnetic disturbance detection method is needed in order to use geomagnetic information. Firstly, in this paper, the availability of geomagnetic information in Japan is investigated by field measurement work. Then, a new magnetic disturbance detection method which is better than the conventional method is proposed. The basic function of the proposed method is tested in actual condition.

This paper proposes the use of on-chip monitor circuits to detect process shift and process spread for post-silicon diagnosis and model-hardware correlation. The amounts of shift and spread allow test engineers to decide the correct test strategy. Monitor structures suitable for detection of process shift and process spread are discussed. Test chips targeting a nominal process corner as well as 4 other corners of “slow-slow”, “fast-fast”, “slow-fast” and “fast-slow” are fabricated in a 65nm process. The monitor structures correctly detects the location of each chip in the process space. The outputs of the monitor structures are further analyzed and decomposed into the process variations in threshold voltage and gate length for model-hardware correlation. Path delay predictions match closely with the silicon values using the extracted parameter shifts. On-chip monitors capable of detecting process shift and process spread are helpful for performance prediction of digital and analog circuits, adaptive delay testing and post-silicon statistical analysis.

The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.

A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.

A variety of ubiquitous computing devices, such as radio frequency identification (RFID) and wireless sensor network (WSN), are generating huge and significant events that should be rapidly processed for business excellence. In this paper, we describe how complex event processing (CEP) technology can be applied to ubiquitous process management based on context-awareness. To address the issue, we propose a method for context-aware event processing using event processing language (EPL) statement. Specifically, the semantics of a situation drive the transformation of EPL statement templates into executable EPL statements. The proposed method is implemented in the domain of ubiquitous cold chain logistics management. With the proposed method, context-aware event processing can be realized to enhance business performance and excellence in ubiquitous computing environments.

Solid-state disks (SSDs) have received much attention as replacements for hard disk drives (HDDs). One of their noticeable advantages is their high-speed read/write operation. To achieve good performance, SSDs have an internal memory hierarchy which includes several volatile memories, such as DRAMs and SRAMs. Furthermore, many SSDs adopt aggressive memory management schemes under the assumption of stable power supply. Unfortunately, the data stored in the volatile memories are lost when the power supplied to SSDs is abruptly shut off. Such power failure is often observed in portable devices. For this reason, it is critical to provide a power failure protection scheme for reliable SSDs. In this work, we propose a power-failure protection scheme for SSDs to increase their reliability. The contribution of our work is three-fold. First, we design a power failure protection circuit which incorporates super-capacitors as well as rechargeable batteries. Second, we provide a method to determine the capacity of backup power sources. Third, we propose a data backup procedure when the power failure occurs. We implemented our method on a real board and applied it to a notebook PC with a contemporary SSD. The board measurement and simulation results prove that our method is robust in cases of sudden power failure.

Critical infrastructures are falsely believed to be safe when they are isolated from the Internet. However, the recent appearance of Stuxnet demonstrated that isolated networks are no longer safe. We observe that a better intrusion detection scheme can be established based on the unique features of critical infrastructures. In this paper, we propose a whitelist-based detection system. Network and application-level whitelists are proposed, which are combined to form a novel cross-layer whitelist. Through experiments, we confirm that the proposed whitelists can exactly detect attack packets, which cannot be achieved by existing schemes.

This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

For opportunistic spectrum access (OSA), spectrum management is a key function to effectively utilize white space without causing harmful interference to incumbent receivers. Geo-location database approaches using radio propagation estimation have been regarded as practical spectrum management methods. However, propagation models inevitably fail to accurately estimate the path loss in actual radio environments, resulting in estimation error of carrier to interference ratio (CIR) of the incumbent receivers. This could prevent white space from being efficiently utilized, because the allowable transmit power of the opportunistic system has to be limited to keep the CIR at the required level. To improve the accuracy of CIR estimation, we propose the new concept of Interference Monitoring which works in combination with spectrum management. In this method, a monitoring node located near the incumbent receivers actually measures both the interference signals and the incumbent signals. Using the measurement results, the CIR estimates are corrected based on the minimum mean square error (MMSE) criterion. The proposed Interference Monitoring can be extended to establish cooperation among multiple monitoring nodes and thus spatial diversity. Analytical evaluations assuming a simple cellular system model show that Interference Monitoring can more accurately estimate CIR, and thus it can significantly increase the allowable transmit power. For an urban macro cell, Interference Monitoring with a single node achieved about a 6.5 dB increase in the transmit power; Cooperative Interference Monitoring with 4 nodes achieved about a 13.5 dB increase. Thus, Interference Monitoring-based spectrum management can maximize opportunities for white space utilization without imposing additional interference to the incumbent system.

In situ UV-vis. absorption spectra of cytochrome c adsorbed on ITO electrode was observed with slab optical waveguide spectroscopy combining pulse potential step (PPS) between 0.3 and -0.45 V vs. Ag/AgCl. The amount of cytochrome c adsorbed on ITO electrode was estimated from the amount of coulomb of the peaks in cyclic voltammogram to be about a monolayer coverage in this experimental condition. Spectral change between oxidized and reduced cytochrome c by PPS was finished in about 20 msec with phosphate buffer solution. The results strongly proved that SOWG spectroscopy should be effective for in situ observation of ET reaction kinetics of surface adsorbed molecules.

To obtain an ultra-short high-intensity pulse source, we investigated the amplification characteristics of two types of pulses (dissipative soliton and stretched pulses) produced by our Yb-doped fiber laser oscillator. Our results show that the dissipative soliton pulse can be amplified with less deterioration than the stretched pulse.

We report a trial of 100-GS/s optical quantization with 5-bit resolution using soliton self-frequency shift (SSFS) and spectral compression. We confirm that 100-GS/s 5-bit optical quantization is realized to quantize a 5.0-GHz sinusoid electrical signal in simulation. In order to experimentally verify the possibility of 100-GS/s 5-bit optical quantization, we execute 5-bit optical quantization by using two sampled signals with 10-ps intervals.

This paper proposes a pipeline analog-to-digital converter (ADC) with non-binary encoding technique based on β-expansion. By using multiply-by-β switched-capacitor (SC) multiplying digital-to-analog converter (MDAC) circuit, our proposed ADC is composed by radix-β (1 < β < 2) 1 bit pipeline stages instead of using the conventional radix-2 1.5 bit/1 bit pipeline stages to realize non-binary analog-to-digital conversion. Also with proposed β-value estimation algorithm, there is not any digital calibration technique is required in proposed pipeline ADC. The redundancy of non-binary ADC tolerates not only the non-ideality of comparator, but also the mismatch of capacitances and the gain error of operational amplifier (op-amp) in MDAC. As a result, the power hungry high gain and wide bandwidth op-amps are not necessary for high resolution ADC, so that the reliability-enhanced pipeline ADC with simple amplifiers can operate faster and with lower power. We analyse the β-expansion of AD conversion and modify the β-encoding technique for pipeline ADC. In our knowledge, this is the first proposal architecture for non-binary pipeline ADC. The reliability of the proposed ADC architecture and β-encoding technique are verified by MATLAB simulations.

A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

A design methodology for implementation of low-noise switched-capacitor low-pass filter (SC LPF) with small capacitance spread is proposed. The proposed method is focused on the reduction of operational amplifier noise transfer gain at low frequencies and the reduction of total capacitance. A new SC LPF topology is proposed in order to adapt the correlated double sampling and charge scaling technique at the same time. Design examples show that proposed filter reduces the total capacitance by 65% or more compared to the conventional one without having significant increase in noise transfer gain.

In our privious paper, we proposed an algorithm that determines delay times of a timed Petri net from the structural information of a signaling pathway, but Petri net structures containing cycles and inhibitory arcs were not considered. This paper provides conditions for cycle-contained Petri nets to have reasonable delay times. Furthermore, handling of inhibitory arcs are discussed in terms of the reaction rate of inhibitory interaction in signaling pathway, especially the conversion process of Petri net with inhibitory arc to the one without inhibitory arc is given.

Context awareness is one of the ultimate goals of ubiquitous computing, and spatial information plays an important role in building context awareness. In this paper, we propose a new interoperable spatial information model, which is based on ucode relation (ucR) and Place Identifier (PI), for realizing ubiquitous spatial infrastructure. In addition, we propose a design environment for spatial information database using our model. Our model is based on ucode and its relation. ucode is 128 bits number and the number itself has no meaning. Hence, it is difficult to manage the relation between ucodes without using a tool. Our design environment provides to describe connection between each ucode visually and is able to manipulate data using the target space map interactively. To evaluate the proposed model and environment, we designed three spaces using our tool. In addition, we developed a web application using our spatial model. From evaluation, we have been showed that our model is effective and our design environment is useful to develop our spatial information model.

A garbage collector relieves programmers from manual memory management and improves productivity and program reliability. However, there are many other finite system resources that programmers must manage by themselves, such as sockets and database connections. Growing resource leaks can lead to performance degradation and even program crashes. This paper presents the automatic resource collection approach called Resco (RESource COllector) to tolerate non-memory resource leaks. Resco prevents performance degradation and crashes due to resource leaks by two steps. First, it utilizes monitors to count resource consumption and request resource collections independently of memory usage when resource limits are about to be violated. Second, it responds to a resource collection request by safely releasing leaked resources. We implement Resco based on a Java Virtual Machine for Java programs. The performance evaluation against standard benchmarks shows that Resco has a very low overhead, around 1% or 3%. Experiments on resource leak bugs show that Resco successfully prevents most of these programs from crashing with little increase in execution time.

A reliable detection of atrial fibrillation (AF) in Electrocardiogram (ECG) monitoring systems is significant for early treatment and health risk reduction. Various ECG mining and analysis studies have addressed a wide variety of clinical and technical issues. However, there is still room for improvement mostly in two areas. First, the morphological descriptors not only between different patients or patient clusters but also within the same patient are potentially changing. As a result, the model constructed using an old training data no longer needs to be adjusted in order to identify new concepts. Second, the number and types of ECG parameters necessary for detecting AF arrhythmia with high quality encounter a massive number of challenges in relation to computational effort and time consumption. We proposed a mixture technique that caters to these limitations. It includes an active learning method in conjunction with an ECG parameter customization technique to achieve a better AF arrhythmia detection in real-time applications. The performance of our proposed technique showed a sensitivity of 95.2%, a specificity of 99.6%, and an overall accuracy of 99.2%.

This paper introduces new FPGA design of user-monitoring system for power management of PC display. From the camera readings the system detects whether the user looks at the screen or not and produces signals to control the display backlight. The system provides over 88% eye detection accuracy at 8f/s image processing rate. We describe new eye-tracking algorithm and hardware and present the results of its experimental evaluation in prototype display power management system.