We propose a proof-of-concept of a switchable multi-frequency MMIC (monolithic microwave integrated circuit) oscillator device, operating in the 60 GHz millimeter wave band, which is implemented in GaAs p-HEMT transistor technology. Oscillators that can switch between two frequencies have been designed, fabricated and evaluated. The oscillator uses a cross-coupled FET topology, combined with a bent asymmetric coplanar stripline for the resonator, and a switched-capacitor for the frequency switching components. The oscillator generates two oscillations at f/2 and f where f is the target frequency of around 60 GHz. The switchable oscillator has been demonstrated for the range of frequency from 44 GHz to 68.9 GHz. Moreover, the designed oscillator exhibits a wide-band negative resistance property that allows fabricating switchable oscillators covering the 50 to 75 GHz V-band. An evaluated switchable oscillator delivers -17.09 dBm and -13.72 dBm output power at 62.45 GHz and 64.78 GHz, for a supplied power of 40.6 mW and 39.1 mW, respectively.

A physics-based equivalent circuit model of the ceramic capacitor is proposed, which can reproduce frequency characteristics of its impedance including the often observed yet hitherto physically unexplained kinks appearing above the primary series resonance frequency. The model can also account for parasitic effects of external inductances. In order to efficiently analyze and gain engineering insight into ceramic capacitors with a large number of metallic laminae, a two-dimensional method of moments is developed that treats the laminar structure as a uniform, effective medium. It turns out that the primary resonance and the kinks can be well understood and modeled by a lossy transmission line stub with a drastic wavelength reduction. The capacitor model is completed by adding components describing the skin effect and external inductances. The modeled impedance stays within a 4% margin of error up to 5 GHz. The proposed model could greatly improve the accuracy of power distribution network simulation.

Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65 nm CMOS process. The ADC has an input capacitance of 180 fF and occupies an active area of 0.03 mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.

This paper proposes a sensing system for a behavior detection system using an ultrasonic oscillosensor and an air pressure sensor. The ultrasonic oscillosensor sensor has a cylindrical tank filled with water. It detects the vibration of the target object from the signal reflected from the water surface. This sensor can detect a biological vibration by setting to the bottom bed frame. The air pressure sensor consists of a polypropylene sheet and an air pressure sensor, and detects the pressure information by setting under the bed's mattress. An increase (decrease) in the load placed on the bed is detected by the increase (decrease) in the pressure of the air held in the tube attached to the sheet. We propose a behavior detection system using both sensors, complementally. The system recognizes three states (nobody in bed, keeping quiet in bed, moving in bed) using both sensors, and we detect the behavior before getting out of bed by recognized these states. Fuzzy logic plays a primary role in the system. As the fundamental experiment, we applied the system to five healthy volunteers, the system successfully recognized three states, and detected the behavior before getting out of bed. As the clinical experiment, we applied the system to four elderly patients with dementia, the system exactly detected the behavior before getting out of the bed with enough time for medical care support.

This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore, total memory requirements can be minimized.

With DCT coding, block artifact and mosquito noise degradations appear in decoded pictures. The control of post filtering is important to reduce degradations without causing side effects. Decoding information is useful, if the filter is inside or close to the encoder; however, it is difficult to control with independent post filtering, such as in a display. In this case, control requires the estimation of the artifact from only the decoded picture. In this work, we describe an estimation method that determines the mosquito noise block and level. In this method, the ratio of spatial activity is taken between the mosquito block and the neighboring flat block. We test the proposed method using the reconstructed pictures which are coded with different quantization scales. We recognize that the results are mostly reasonable with the different quantizations.

Developing a non-intrusive packet-layer model is required to passively monitor the quality of experience (QoE) during service. We propose a packet-layer model that can be used to estimate the video quality of IPTV using quality parameters derived from transmitted packet headers. The computational load of the model is lighter than that of the model that takes video signals and/or video-related bitstream information such as motion vectors as input. This model is applicable even if the transmitted bitstream information is encrypted because it uses transmitted packet headers rather than bitstream information. For developing the model, we conducted three extensive subjective quality assessments for different encoders and decoders (codecs), and video content. Then, we modeled the subjective video quality assessment characteristics based on objective features affected by coding and packet loss. Finally, we verified the model's validity by applying our model to unknown data sets different from training data sets used above.

MOS capacitors with Si-implanted thermal oxide and CVD deposited oxide of 30 nm thickness were fabricated for applications of non-volatile memory and electroluminescence devices. Current-voltage (I-V) and I-V hysteresis characteristics were measured, and the hysteresis window (HW) and the integrated charge of HW (ICHW) extracted from the hysteresis data were discussed. The HW characteristics of high Si dose samples showed the asymmetrical double-peaks curves with the hump in both tails. The ICHW almost converged after the 4th cycle and had the voltage sweep speed dependence. All +ICHW and -ICHW characteristics were closely related to the static (+I)-(+VG) and (-I)-(-VG) curves, respectively. For the high Si dose samples, the clear hump currents in the static I-VG characteristics contribute to lower the rising voltage and to steepen the ICHW increase, which correspond to the large stored charge in the oxide.

IEEE 802.15.4 is a new standard, uniquely designed for low rate wireless personal area networks (LR-WPANs). It targets ultra-low complexity, cost, and power, for low-data-rate wireless connectivity. However, one of the main problems of this new standard is its insufficient, and inefficient, media access control (MAC) for priority data. This paper introduces an extended contention access period (XCAP) concept for priority packets, also an traffic adaptive contention differentiation utilizing the XCAP (TACDX). The TACDX determines appropriate transmission policy alternatively according to the traffic conditions and type of packet. TACDX achieves not only enhanced transmission for priority packets but it also has a high energy efficiency for the overall network. The proposed TACDX is verified with simulations to measure the performances.

This letter presents a new quadrature voltage-controlled oscillator (QVCO) consisting of two n-core Colpitts voltage-controlled oscillators (VCOs) with a tail inductor. The VCOs are used as a single-ended injected injection-locked frequency divider (ILFD). The output of the tail inductor in one ILFD is injected into the injection node in the other ILFD and vice versa. The proposed QVCO has been implemented in the 0.18 µm CMOS technology. At the supply voltage of 1.0 V, the power consumption is 1.8 mW. The free-running frequency is tunable from 4.68 GHz to 5.03 GHz as the tuning voltage is varied from 0.0 V to 1.8 V. The measured phase noise is -113.58 dBc/Hz at the 1 MHz frequency offset from the oscillation frequency of 5.03 GHz and the figure of merit (FOM) of the QVCO is -185.06 dBc/Hz.

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.

This paper presents a fuzzy-based path selection method for improving the security level, in which each cluster chooses paths based on the detection power of false data and energy efficiency.

The electromagnetic fields emitted from an electrostatic discharge (ESD) event occurring between charged metals cause seriously damage high-tech equipment. In order to clarify the generation mechanism of such ESD fields and also to reduce them, we previously proposed a finite-difference time-domain (FDTD) algorithm based on a delta-gap feeding method and a frequency dispersion characteristic formula (Naito's formula) of ferrite material for simulating the ESD fields due to a spark between the charged metals with ferrite core attachment. In the present study, by integrating the above FDTD algorithm and a spark-resistance formula, we simulated both of the ESD itself and the resultant fields for the metal bars with ferrite core attachment, and demonstrated that the core attachment close to the spark gap suppresses the magnetic field level. This finding was also validated via 6-GHz wide-band measurement of the magnetic near-field.

This Letter proposes an optimal gain filter for the perceptual acoustic echo suppressor. We designed an optimally-modified log-spectral amplitude estimation algorithm for the gain filter in order to achieve robust suppression of echo and noise. A new parameter including information about interferences (echo and noise) of single-talk duration is statistically analyzed, and then the speech absence probability and the a posteriori SNR are judiciously estimated to determine the optimal solution. The experiments show that the proposed gain filter attains a significantly improved reduction of echo and noise with less speech distortion.

This paper proposes a novel service configuration approach that can realize dynamic critical Quality of Service (QoS) adaptation to ever-changing and resource-limited ubiquitous computing environments. In the approach, service configuration is reduced to a Fuzzy Control System (FCS) which aims to achieve critical QoS variations on minimal level with less power cost. Two configuration strategies, service chain reconfiguration and QoS parameters adjustment, along with a configuration algorithm, are implemented to handle different types of QoS variations. A self-optimizing algorithm is designed to enhance the adaptation of the FCS. Simulation results validate the proposed approach.

There has been a wide-ranging discussion on the issue of content copyright protection in digital content distribution systems. Fiat and Tassa proposed the framework of dynamic traitor tracing. Their framework requires dynamic computation transactions according to the real-time responses of the pirate, and it presumes real-time observation of content redistribution. Therefore, it cannot be simply utilized in an application where such an assumption is not valid. In this paper, we propose a new scheme that provides the advantages of dynamic traitor tracing schemes and also overcomes their problems.

A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.

Considering rapid increase of recent highly organized and sophisticated malwares, practical solutions for the countermeasures against malwares especially related to zero-day attacks should be effectively developed in an urgent manner. Several research activities have been already carried out focusing on statistic calculation of network events by means of global network sensors (so-called macroscopic approach) as well as on direct malware analysis such as code analysis (so-called microscopic approach). However, in the current research activities, it is not clear at all how to inter-correlate between network behaviors obtained from macroscopic approach and malware behaviors obtained from microscopic approach. In this paper, in one side, network behaviors observed from darknet are strictly analyzed to produce scan profiles, and in the other side, malware behaviors obtained from honeypots are correctly analyzed so as to produce a set of profiles containing malware characteristics. To this end, inter-relationship between above two types of profiles is practically discussed and studied so that frequently observed malwares behaviors can be finally identified in view of scan-malware chain.

An on-chip CMOS preamplifier for direct signal readout from an electret capacitor microphone has been designed with high immunity to common-mode and supply noise. The Gm-Opamp-RC based high impedance preamplifier helps to remove all disadvantages of the conventional JFET based amplifier and can drive a following switched-capacitor sigma-delta modulator in order to realize a compact digital electret microphone. The proposed chip is designed based on 0.18 µm CMOS technology, and the simulation results show 86 dB of dynamic range with 4.5 µVrms of input-referred noise for an audio bandwidth of 20 kHz and a total harmonic distortion (THD) of 1% at 90 mVrms input. Power supply rejection ratio (PSRR) and common-mode rejection ration (CMRR) are more than 95 dB at 1 kHz. The proposed design dissipates 125 µA and can operate over a wide supply voltage range of 1.6 V to 3.3 V.

Electrical modeling for surface-mount passive components is proposed. In order to accurately capture parasitic inductance, the proposed 2-port model accounts for surrounding ground layer configurations of the print circuit board (PCB) on which the component is mounted. Our model retains conventional modeling paradigm in which component suppliers provide their customers with simulation models characterized independently of the customers' PCB. We also present necessary corrections that compensate magnetic coupling between the separated models. Impedance and its anti-resonant frequency of two power distribution networks are experimentally analyzed being non-separated modeling as the reference. The proposed model achieved very good match with the reference result reducing 7-34% error of the conventional model to about 2%.