This paper introduces a fast image denoising algorithm by estimating noise parameters without prior information about the noise. Under the assumption that additive noise has a Gaussian distribution, the noise parameters were estimated from an observed degraded image, and were used to define the constraints of a noise detection process that was coupled with a Markov random field (MRF). In addition, an adaptive modified weighted Gaussian filter with variable window sizes defined by the constraints on noise detection was used to control the degree of smoothness of the reconstructed image. Experimental results demonstrate the capability of the proposed algorithm.

In this paper, we consider the Reed-Solomon codes over Fqm with evaluations in a subfield Fq. By the “virtual extension”, we can embed these codes into homogeneous interleaved Reed-Solomon codes. Based on this property and the collaborative decoding algorithm, a new probabilistic decoding algorithm that can correct errors up to $rac{m}{m+1}(n-k)$ for these codes is proposed. We show that whether the new decoding algorithm fails or not is only dependent on the error. We also give an upper bound on the failure probability of the new decoding algorithm for the case s=2. The new decoding algorithm has some advantages over some known decoding algorithms.

Network coding on the physical-layer has recently been widely discussed as a potentially promising solution to the wireless access problem in a relay network. However, the existing research on physical-layer network coding (PNC), usually assumes that the symbol timing of the nodes is fully synchronized and hardly investigates the unavoidable symbol timing errors. Similar to many telecommunication systems, symbol timing plays a critical role in PNC and precise alignment has to be provided for the encoding. In this work, we propose a novel symbol timing algorithm with a low oversampling factor (samples per symbol) based on the a priori knowledge of the transmitted pulse shape. The proposed algorithm has the dual advantages of the low oversampling rate and high precision. The mean square error (MSE) performance is verified by simulations to be at least one order of magnitude better than that of the conventional optimum phase (OP) algorithm for a signal noise ratio (SNR) greater than 5dB.

The authors propose “Disk-repeater” as a new structure alternative to the conventional resonator repeater. Disk-repeater has a simple structure comprised of just copper plates and wire, non-resonant structure. First, coupling coefficients are measured as functions of disk diameter and wire length to characterize the basic performance of Disk-repeater. It is explained by several experimental evidences that Disk-repeater and resonator are not magnetically coupled but electrically coupled. It is also shown that the transmission distance extends dramatically longer than that of conventional resonator repeater. Further, two-dimensional arrangement, where multiple disks are connected, shows very high efficiency and uniform transmission characteristic regardless of positions of receiving resonator. Disk-repeater gives possibility of unprecedented versatile application with the simple structure.

This paper describes the circuit design and measurement results of a new GaAs-HBT RF power detector proposed for use in WiMAX and wireless LAN transmitter applications. The detector, which is based on a simple current-mirror topology, occupies a small die area. It is, therefore, not only easy to implement together with a GaAs-HBT power amplifier, but can also offer approximately logarithmic (linear-in-dB) characteristics. Because it can also be driven with small voltage amplitudes, it is suitable for base-terminal monitoring at an HBT power stage. When the detector is used as a base-terminal power monitor, an appropriate base resistance added to the detection HBT effectively suppresses frequency dispersion of the detected voltage characteristics. Measurements of a prototype detector incorporated into a single-stage HBT power amplifier fabricated on the same die are as follows. The detector is capable of delivering a detected voltage of 0.35-2.5 V with a slope of less than 0.17 V/dB over a 4-to-24-dBm output power range at 3.5 GHz while drawing a current of less than 1.8 mA from a 2.85-V supply. While satisfying a log conformance error of less than 1 dB over an amplifier output power range from 4 dBm to 24 dBm, it can also suppress the detected power dispersion within 0.18 dB at approximately 15 dBm of output power over a 3.1-3.9-GHz-wide frequency range. This dispersion value is approximately one-tenth that of a conventional collector-terminal-monitor-type diode detector.

In this paper, a self-recoverable, frequency-aware and cost-effective robust latch (referred to as RFC) is proposed in 45nm CMOS technology. By means of triple mutually feedback Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset (SEU), i.e. particle striking induced logic upset, regardless of the energy of the striking particle. The proposed robust latch offers a much wider spectrum of working clock frequency on account of a smaller delay and insensitivity to high impedance state. The proposed robust latch performs with lower costs regarding power and area than most of the compared latches. SPICE simulation results demonstrate that the area-power-delay product is 73.74% saving on average compared with previous radiation hardened latches.

A 300-GHz hetero-generous package solution with a combination of a polyimide microstrip-to-waveguide transition on low-temperature co-fired ceramic (LTCC) is presented. To assemble three parts — a metal back-short, polyimide transition, and LTCC substrate integrated waveguide (SIW) — a ridged microstructure beside the microstrip probe was implemented to reduce the air gap on the broadwall of a back-short. A back-to-back transition exhibited an insertion loss of 4.4 dB at 300 GHz and 49-GHz bandwidth with less than a 10-dB return loss. By evaluating loss of the microstrip line and SIW, we estimated the loss for a single transition, which was 0.9 dB at 300 GHz. The probe transition with ridged metal successfully suppressed the unwanted dip in transmission characteristics and eased the difficulty in assembly. The compact transition is easy to integrate in an antenna-in-package with an MMIC chip by combining suitable substrate materials for the transition and package.

To analyze the structure of a set of high-dimensional perfect sequences over a composition algebra over R, we developed the theory of Fourier transforms of the set of such sequences. We define the discrete cosine transform and the discrete sine transform, and we show that there exists a relationship between these transforms and a convolution of sequences. By applying this property to a set of perfect sequences, we obtain a parameterization theorem. Using this theorem, we show the equivalence between the left perfectness and right perfectness of sequences. For sequences of real numbers, we obtain the parameterization without restrictions on the parameters.

The purpose of this work is to reduce the redundant coding process with the tradeoff between the encoding complexity and coding efficiency in HEVC, especially for high resolution applications. Therefore, a CU depth prediction algorithm is proposed for motion estimation process of HEVC. At first, an efficient CTU depth prediction algorithm is proposed to reduce redundant depth. Then, CU size termination and skip algorithm is proposed based on the neighboring block depth and motion consistency. Finally, the overall algorithm, which has excellent complexity reduction performance for high resolution application is proposed. Moreover, the proposed method achieves steady performance, and it can significantly reduce the encoding time in different environment configuration and quantization parameter. The simulation experiment results demonstrate that, in the RA case, the average time saving is about 56% with only 0.79% BD-bitrate loss for the high resolution, and this performance is better than the previous state of the art work.

Outsourcing IC design and fabrication is one of the effective solutions to reduce design cost but it may cause severe security risks. Particularly, malicious outside vendors may implement Hardware Trojans (HTs) on ICs. When we focus on IC design phase, we cannot assume an HT-free netlist or a Golden netlist and it is too difficult to identify whether a given netlist is HT-free or not. In this paper, we propose a score-based hardware-trojans identifying method at gate-level netlists without using a Golden netlist. Our proposed method does not directly detect HTs themselves in a gate-level netlist but it detects a net included in HTs, which is called Trojan net, instead. Firstly, we observe Trojan nets from several HT-inserted benchmarks and extract several their features. Secondly, we give scores to extracted Trojan net features and sum up them for each net in benchmarks. Then we can find out a score threshold to classify HT-free and HT-inserted netlists. Based on these scores, we can successfully classify HT-free and HT-inserted netlists in all the Trust-HUB gate-level benchmarks and ISCAS85 benchmarks as well as HT-free and HT-inserted AES gate-level netlists. Experimental results demonstrate that our method successfully identify all the HT-inserted gate-level benchmarks to be “HT-inserted” and all the HT-free gate-level benchmarks to be “HT-free” in approximately three hours for each benchmark.

This letter investigates the circularity of fractional Fourier transform (FRFT) coefficients containing noise only, and proves that all coefficients coming from white Gaussian noise are circular via the discrete FRFT. In order to use the spectrum kurtosis (SK) as a Gaussian test to check if linear frequency modulation (LFM) signals are present in a set of FRFT points, the effect of the noncircularity of Gaussian variables upon the SK of FRFT coefficients is studied. The SK of the α th-order FRFT coefficients for LFM signals embedded in a white Gaussian noise is also derived in this letter. Finally the signal detection algorithm based on FRFT and SK is proposed. The effectiveness and robustness of this algorithm are evaluated via simulations under lower SNR and weaker components.

There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modeling techniques. Low-power high-speed wireless data transfer at 11Gb/s and 19pJ/bit and a 7-pJ/bit ultra-low-power transceiver chipset are presented.

A wide-bandwidth fundamental mixer operating at a frequency above 110GHz for precise spectrum analysis was developed using the InP HEMT technology. A single-ended resistive mixer was adopted for the mixer circuit. An IF amplifier and LO buffer amplifier were also developed and integrated into the mixer chip. As for packaging into a metal block module, a flip-chip bonding technique was introduced. Compared to face-up mounting with wire connections, flip-chip bonding exhibited good frequency flatness in signal loss. The mixer module with a built-in IF amplifier achieved a conversion gain of 5dB at an RF frequency of 135GHz and a 3-dB bandwidth of 35GHz. The mixer module with an LO buffer amplifier operated well even at an LO power of -20dBm.

The amount of seasonings used during food preparation is quite important information for modern people to enable them to cook delicious dishes as well as to take care for their health. In this paper, we propose a near real-time automated system for measuring and recording the amount of seasonings used during food preparation. Our proposed system is equipped with two devices: electronic scales and a camera. Seasoning bottles are basically placed on the electronic scales in the proposed system, and the scales continually measure the total weight of the bottles placed on them. When a chef uses a certain seasoning, he/she first picks up the bottle containing it from the scales, then adds the seasoning to a dish, and then returns the bottle to the scales. In this process, the chef's picking and returning actions are monitored by the camera. The consumed amount of each seasoning is calculated as the difference in weight between before and after it is used. We evaluated the performance of the proposed system with experiments in 301 trials in actual food preparation performed by seven participants. The results revealed that our system successfully measured the consumption of seasonings in 60.1% of all the trials.

Many public cloud datacenters have adopted the Edge-Overlay model which supports virtual switch-based network virtualization using IP tunneling. However, software-implemented virtual switches can cause performance degradation because the packet processing load can concentrate on a particular CPU core. As a result, such load concentration decreases and destabilizes the performance of virtual networks. Although multi-queue functions like Receive Side Scaling (RSS) can distribute the load onto multiple CPU cores, they still have performance problems such as IRQ core collision between priority flows as well as competitive resource use between host and guest machines for received packet processing. In this paper, we propose Virtual Switch Extension (VSE) that adaptively determines CPU core assignment for SoftIRQ to prevent performance degradation. VSE supports two types of SoftIRQ core selection mechanisms, on-the-fly or predetermined. In the on-the-fly mode, VSE selects a SoftIRQ core based on current CPU load to exploit low-loaded CPU resources. In the predetermined mode, SoftIRQ cores are assigned in advance to differentiate the performance of priority flows. This paper describes a basic architecture and implementation of VSE and how VSE assigns a SoftIRQ cores. Moreover, we evaluate fundamental throughput of various CPU assignment models in the predetermined mode. Finally, we evaluate the performance of a priority VM in two VM usecases, the client-usecase which is receive-oriented and the router-usecase which performs bi-directional communications. In the client-usecase, the throughput of the priority VM was improved by 31% compared with RSS when the priority VM had one dedicated core. In the router-usecase, the throughput was improved by 29% when three dedicated cores were provided for the VM.

Crowd collectiveness, i.e., a quantitative metric for collective motion, has received increasing attention in recent years. Most of existing methods build a collective network by assuming each agent in the crowd interacts with neighbors within fixed radius r region or fixed k nearest neighbors. However, they usually use a universal r or k for different crowded scenes, which may yield inaccurate network topology and lead to lack of adaptivity to varying collective motion scenarios, thereby resulting in poor performance. To overcome these limitations, we propose a compressive sensing (CS) based method for measuring crowd collectiveness. The proposed method uncovers the connections among agents from the motion time series by solving a CS problem, which needs not specify an r or k as a priori. A descriptor based on the average velocity correlations of connected agents is then constructed to compute the collectiveness value. Experimental results demonstrate that the proposed method is effective in measuring crowd collectiveness, and performs on par with or better than the state-of-the-art methods.

The next generation high efficiency video coding (HEVC) standard achieves high performance by extending the encoding block to 64×64. There are some parallel tools to improve the efficiency for encoder and decoder. However, owing to the dependence of the current prediction block and surrounding block, parallel processing at CU level and Sub-CU level are hard to achieve. In this paper, focusing on the spatial motion vector prediction (SMVP) and temporal motion vector prediction (TMVP), parallel improvement for spatio-temporal prediction algorithms are presented, which can remove the dependency between prediction coding units and neighboring coding units. Using this proposal, it is convenient to process motion estimation in parallel, which is suitable for different parallel platforms such as multi-core platform, compute unified device architecture (CUDA) and so on. The simulation experiment results demonstrate that based on HM12.0 test model for different test sequences, the proposed algorithm can improve the advanced motion vector prediction with only 0.01% BD-rate increase that result is better than previous work, and the BDPSNR is almost the same as the HEVC reference software.

Nonnegative matrix factorization (NMF) is an unsupervised technique to represent nonnegative data as linear combinations of nonnegative bases, which has shown impressive performance for source separation. However, its source separation performance degrades when one signal can also be described well with the bases for the interfering source signals. In this paper, we propose a discriminative NMF (DNMF) algorithm which exploits the reconstruction error for the interfering signals as well as the target signal based on target bases. The objective function for training the bases is constructed so as to yield high reconstruction error for the interfering source signals while guaranteeing low reconstruction error for the target source signals. Experiments show that the proposed method outperformed the standard NMF and another DNMF method in terms of both the perceptual evaluation of speech quality score and signal-to-distortion ratio in various noisy environments.

Although sparse coding has emerged as an extremely powerful tool for texture and image classification, it neglects the relationship of coding coefficients from the same class in the training stage, which may cause a decline in the classification performance. In this paper, we propose a novel coding strategy named compact sparse coding for ground-based cloud classification. We add a constraint on coding coefficients into the objective function of traditional sparse coding. In this way, coding coefficients from the same class can be forced to their mean vector, making them more compact and discriminative. Experiments demonstrate that our method achieves better performance than the state-of-the-art methods.

This paper presents an Adapting Block-Propagative Background Subtraction (ABPBGS) designed for Ultra High Definition Television (UHDTV) foreground detection. The main idea is to detect block after block along the objects in order to skip all areas of the image in which there is no moving object. This is particularly interesting for UHDTV when the objects of interest could represent not even 0.1% of the total area. From a seed block which is determined in a previous iteration, the detection will spread along an object as long as it detects a part of that object. A block history map guaranties that each block is processed only once. Moreover, only small blocks are loaded and processed, thus saving computational time and memory usage. The process of each block is independent enough to be easily parallelized. Compared to 9 state-of-the-art works, the ABPBGS achieved the best results with an average global quality score of 0.57 (1 being the maximum) on a dataset of 4K and 8K UHDTV sequences developed for this work. None of the state-of-the-art methods could process 4K videos in reasonable time while the ABPBGS has shown an average speed of 5.18fps. In comparison, 5 of the 9 state-of-the-art methods performed slower on 270p down-scale version of the same videos. The experiments have also shown that for the process an 8K UHDTV video the ABPBGS can divide the memory required by about 24 for a total of 450MB.