This paper presents a novel threshold-based selection scheme to combine adaptive transmit antenna selection with an adaptive quadrature amplitude modulation (AQAM) for a spatial multiplexing (SM) multiple-input multiple-output (MIMO) system with linear receivers in practical uncorrelated and correlated channel conditions. The proposed scheme aims to maximize the average spectral efficiency (ASE) for a given bit error rate (BER) constraint and also to lower the hardware complexity. Our simulations are run on a general MIMO channel model, under the assumption that the channel state information (CSI) is known at the receiver and the adaptive control signaling can be perfectly fed back to the transmitter. We deploy the low rank-revealing QR (LRRQR) algorithm in transmit antenna subset selection. LRRQR is computationally less expensive than a singular value decomposition (SVD) based algorithm while the two algorithms achieve similar error rate performances. We show that both the conventional AQAM scheme (i.e., without adaptive transmit antenna selection) and the SM scheme perform poorly in a highly correlated channel environment. We demonstrate that our proposed scheme provides a well-behaved trade-off between the ASE and BER under various channel environments. The ASE (i.e., throughput) can be maximized with a proper choice of the channel quality threshold and AQAM mode switching threshold levels for a target BER.

This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130 nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability σ (Ids) by 23.2-57.9%.

A guarantee obligation of keeping a Static-Noise-Margin (SNM), a Write-Margin (WRTM), and a cell current (Icell) even against a simultaneous Read/Write (R/W) disturbed access at the same column is required for a 1R/1W (1R/1W) SRAM. We have verified that it is difficult for the previously proposed techniques [1]-[5] so far to meet all the requirements simultaneously without any decrease in Icell or any significant area penalty. In order to address this issue, a new cell design technique for the 1R/1W SRAM cell with 8Tr's has been proposed and demonstrated in a 65 nm CMOS technology. It has been shown that Icell in the R/W disturbed column can be increased by 77% and 195% at Vdd=0.9 V and 0.6 V, respectively, and a cell size can be reduced by 15%, compared with the conventional column-based cell power-terminal bias (VDDM) control [1],[2] assuming that the same Icell of 9 µA at Vdd=0.9 V has to be provided. Compared with the conventional scheme, it has been found that the proposed Write-Bit-Line precharge level (VWBL) control and column-based cell source-terminal bias (VSSM) control can provide a 1.45-times larger SNM for Write-Word-Line (WWL) disturbed cells and a 1.7-fold larger WRTM while keeping the same Icell, respectively.

We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each Vth level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.

Manually collecting contexts of a target word and grouping them based on their meanings yields a set of word senses but the task is quite tedious. Towards automated lexicography, this paper proposes a word-sense discrimination method based on two modern techniques; EM algorithm and principal component analysis (PCA). The spherical Gaussian EM algorithm enhanced with PCA for robust initialization is proposed to cluster word senses of a target word automatically. Three variants of the algorithm, namely PCA, sGEM, and PCA-sGEM, are investigated using a gold standard dataset of two polysemous words. The clustering result is evaluated using the measures of purity and entropy as well as a more recent measure called normalized mutual information (NMI). The experimental result indicates that the proposed algorithms gain promising performance with regard to discriminate word senses and the PCA-sGEM outperforms the other two methods to some extent.

Geographic distributed hash table (DHT) protocols are considered to be efficient for P2P object sharing in mobile ad-hoc networks. These protocols assume that the set of pairs, called indexes, should be distributed among nodes according to the following hashing mapping rule: A key hashes into a geographic coordinate, and the corresponding index is stored at the node closest to the key's hash value. Therefore, when a node changes its position, some indexes have to be redistributed to other nodes in order to keep the hashing mapping rule consistent. The overhead of index redistribution may be high enough to impact the normal lookup operation if each node contains a large number of indexes. In this paper, we propose an efficient lookup protocol, called Double Indirect Access, that dispenses with index redistribution to improve lookup performance. The main idea is to determine the mapping from an index to a node not by the node's position, but by the node's static identifier that is obtained by hashing its MAC address into a geographic coordinate. However, a key lookup request will be routed to some node based on the key's hash value, resulting in failure of locating the index. In Double Indirect Access, the node to which a key lookup request has been routed is named as an indirection server, and it is responsible for relaying the lookup request to the node storing the corresponding index. In order for the indirection server to find out the correct destination node for the lookup request, it maintains a list of nodes' static identifiers whose values (i.e., geographic coordinates) are close to the location of the indirection server. Simulation results show that, when the average number of objects per node is more than 256, our approach is able to reduce the number of packet transmissions by about a half compared to the conventional geographical DHT protocol. It is also shown that, even when the average number of objects per node is about 9-16, the overhead of our approach is comparable with the conventional protocol.

The Self-Organizing Map (SOM) is an unsupervised neural network introduced in the 80's by Teuvo Kohonen. In this paper, we propose a method of simultaneously using two kinds of SOM whose features are different (the nSOM method). Namely, one is distributed in the area at which input data are concentrated, and the other self-organizes the whole of the input space. The competing behavior of the two kinds of SOM for nonuniform input data is investigated. Furthermore, we show its application to clustering and confirm its efficiency by comparing with the k-means method.

All optical analog-to-digital converter consisting of an optical polarization modulator using nonlinear phase shift and switches based on polarization is proposed. The principle of operation is discussed using Jones matrix. Optical polarization states through the system and limit of resolution are evaluated. The resolution is optimized by maintaining the polarization state in the converter and refining the polarization of incident sampling signal. Parallel usage of converter modules is proposed to increase the dynamic range, where cyclic nature of optical phase plays an important roll. Application to photonic routing of our converter is also proposed.

An edge-weighted directed graph is referred to as a network in this paper, and an edge operation is an operation that increases or decreases an edge weight. Decreasing an edge weight from the infinite to a finite value or increasing any edge weight from a finite one to the infinite corresponds to addition or deletion of this edge, respectively. The dynamic shortest path problem (DSPP for short) is defined by "Given any network with a specified vertex (denoted as s), and any sequence of edge operations, construct a shortest path tree of each network obtained by executing those edge operations one by one in the order of the sequence." As an application, fast routing for an interior network using link state protocols, such as OSPF and IS-IS, requires solving DSPP efficiently. In this paper, among as many existing algorithms as possible, including those which execute several edge operations simultaneously, fundamental and/or important algorithms are implemented and their capability is evaluated based on the results of computational experiments.

Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose low power adders that adaptively select supply voltages based on the input vector patterns. First, we apply the proposed scheme to the Ripple Carry Adder (RCA). A prototype design by a 0.18 µm CMOS technology shows that the Adaptive VDD 32-bit RCA achieves 25% power improvement over the conventional RCA with similar speed. The proposed adder cancels out the delay penalty, utilizing two innovative techniques: carry-skip techniques on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. As an expansion to faster adder architectures, we extend the proposal to the Carry-Select Adders (CSA) composed of the RCA sub-blocks. We achieved 24% power improvement on the 128-bit CSA prototype over a conventional design. The proposed scheme also achieves stand-by leakage power reduction--for 32-bit and 128-bit Adaptive RCA and CSA, respectively, 62% and 54% leakage reduction was possible.

In this letter, we propose a new State Model for IPv6 Interfaces, which can help the administrator in determining the status of the IPv6 Interface at any instant. This State Model is superior to the current model as it provides additional information as to why an IPv6 Interface is unavailable for performing the provisioned service and, it is also flexible to define new Secondary State and Secondary State Qualifiers in the future. This State Model helps the administrator to decide what actions he may need to take to bring the Interface UP. Ths State Model is based on the Control State Machine implemented in the Samsung's IPv6 Protocol Stack.

This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below 0.5 LSB and that the settling time after the output current mirror is below 12 ns. Although the proposed IDAC architecture was designed for a BMLD chip, the design concept is generic and can be applied for developing other monotonic high-speed current-mode DACs.

In this paper, we present a general object tracking method based on a newly proposed pixel-wise clustering algorithm. To track an object in a cluttered environment is a challenging issue because a target object may be in concave shape or have apertures (e.g. a hand or a comb). In those cases, it is difficult to separate the target from the background completely by simply modifying the shape of the search area. Our algorithm solves the problem by 1) describing the target object by a set of pixels; 2) using a K-means based algorithm to detect all target pixels. To realize stable and reliable detection of target pixels, we firstly use a 5D feature vector to describe both the color ("Y, U, V") and the position ("x, y") of each pixel uniformly. This enables the simultaneous adaptation to both the color and geometric features during tracking. Secondly, we use a variable ellipse model to describe the shape of the search area and to model the surrounding background. This guarantees the stable object tracking under various geometric transformations. The robust tracking is realized by classifying the pixels within the search area into "target" and "background" groups with a K-means clustering based algorithm that uses the "positive" and "negative" samples. We also propose a method that can detect the tracking failure and recover from it during tracking by making use of both the "positive" and "negative" samples. This feature makes our method become a more reliable tracking algorithm because it can discover the target once again when the target has become lost. Through the extensive experiments under various environments and conditions, the effectiveness and efficiency of the proposed algorithm is confirmed.

Transitions between a post-wall waveguide and a microstrip line are proposed as the key components for cost-effective millimeter-wave modules. A transition with a coaxial structure is investigated for LTCC laminated layers and 11.3% bandwidth for the reflection smaller than -15 dB is realized in 60 GHz band. The overall connector loss with 1 cm post-wall would be about 0.8 dB. The degradation due to fabrication error is also assessed. The transition in LTCC substrate fulfills electrical and manufacturing demands in millimeter-wave bands.

Recently, research on parallel processing systems is very active, and many complex topologies have been proposed. A burnt pancake graph is one such topology. In this paper, we prove that a faulty burnt pancake graph with degree n has a fault-free Hamiltonian cycle if the number of the faulty elements is n-2 or less, and it has a fault-free Hamiltonian path between any pair of nonfaulty nodes if the number of the faulty elements is n-3 or less.

We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90% of RTL simulation in a multimedia SoC (System-on-Chip) design.

This paper presents two steganographic methods for JPEG2000 still images which approximately preserve histograms of discrete wavelet transform coefficients. Compared with a conventional JPEG2000 steganography, the two methods show better histogram preservation. The proposed methods are promising candidates for secure JPEG2000 steganography against histogram-based attack.

MC-CDMA is an attractive multi-access method for the next generation high-speed mobile communication systems. The uplink transmission performance is limited by the multi-access interference (MAI) from other users since all users share the same bandwidth. Adaptive antenna array can be used to suppress the MAI and to improve the uplink transmission performance. In this paper, we propose a frequency-domain adaptive antenna array for multi-code MC-CDMA. The proposed frequency-domain adaptive antenna array uses a simple normalized LMS (NLMS) algorithm. Although the NLMS algorithm is used, very fast weight convergence within one MC-CDMA symbol duration is achieved since the weight updating is possible as many times as the number of subcarriers within one MC-CDMA symbol duration.

In this letter, the effects of transmit beamforming on downlink performance in DS-CDMA communication systems are examined. We present a simple-to-use expression for the conditional instantaneous SINR after Rake combining. Assuming BPSK modulation, the performance of average bit error rate is evaluated. We compare the average BER performance obtained by different beamforming methods under frequency selective multipath fading channels.

We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2 Mb test device has been fabricated on 130 nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1 ns row-access time is achieved and 250 MHz operation can be realized by using 2 bank 8 b-burst mode.