In this letter, we propose a novel subsampling based image watermark sequentially embedding scheme to reduce the risk of common permutation attack. The image is still perceptual after watermarking, and experimental results also show its effectiveness and robustness.

The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.

A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.

Currently, Mobile IPv6 (MIPv6) working group of Internet Engineering Task Force (IETF) recommends to execute the Binding Update (BU) using Return Routability (RR) procedure. However, the RR procedure doesn't entirely satisfy the security requirements of MIPv6. The previous BU protocols are also likely to reduce the efficiency since they iterate entirely BU protocol courses in Pico/Micro cellular environment in which it occurs frequently handoff or handover and some protocols don't consider that the Correspondent Node (CN) is movable node and has the limited resources. In this paper we propose the ETBU protocol, which is based on Cryptographically Generated Address (CGA) to provide mutual authentication between nodes; it considers that the CN is a movable node. This protocol doesn't require a Mobile Node (MN) to create a signature each time it obtains a new Care-of Address (CoA) unlike the previous CGA-based BU protocol. An MN and its CN issue the ticket to minimize the computing costs that need to calculate CGA. Also, the ETBU protocol minimizes the loss of traffic using smooth handoff or handover. A performance analysis shows that the scheme provides the security as much as the previous BU protocols and more efficiency than them in case that each node obtains the ticket. Therefore, the proposed ETBU protocol can be applied easily to the mobile network environments.

We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90% of RTL simulation in a multimedia SoC (System-on-Chip) design.

Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced by register relocation maintaining the circuit behavior and topology. In this paper, we propose a gate-level register relocation method to reduce the minimum feasible clock period. The proposed method is a greedy local circuit modification method. We prove that the proposed method achieves the clock period achieved by retiming with delay decomposition, if the delay of each element in the circuit is unique. Experiments show that the computation time of the proposed method and the number of registers of a circuit obtained by the proposed method are smaller than those obtained by the retiming method in the conventional synchronous framework.

We propose a new tableau construction which builds an FSM, instead of a Kripke structure, from a formula in a class of temporal logic named ASTL. This FSM is a maximal model of the formula under the preorder derived from simulation relations. Additionally, we propose a method using the tableaus to build controllers in a certain topology of interconnected FSMs. We can use ASTL to describe the desired behaviors of the control system. This method is applicable to generating digital circuits. Moreover, this method accepts a wider range of specifications than conventional methods.

This paper deals with WF-net based modeling and verification of interorganizational workflows (interworkflows for short) based on the protocol of WfMC. In the protocol, there are three patterns of interoperability: Chained, Nested, and Parallel synchronized; and an interworkflow is constructed by using those interoperability patterns. We first give a WF-net based modeling method. In this modeling method, the three interoperability patterns are respectively expressed in terms of WF-nets. They enable us to model a given interworkflow as a WF-net by connecting WF-nets representing its constituent workflows. We also indicate that if free choice WF-nets are connected by means of any combination of the three patterns then the resultant WF-net is asymmetric choice. Next we discuss verification of WF-nets obtained through the modeling method. Intuitively, a WF-net is said to be sound if, for any case, the initial state is always transformed to the final state. Unfortunately, even if every constituent WF-net is sound FC, the resultant WF-net is not always sound. We give a sufficient condition of non-soundness checkable in polynomial time. We also show that if they are connected by only the Nested pattern then the resultant WF-net is sound.

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

For more efficient data transmissions, a new MLP/BP-based channel equalizer is proposed to compensate for multi-path fading in wireless applications. In this work, for better system performance, we apply the soft output and the soft feedback structure as well as the soft decision channel decoding. Moreover, to improve packet error rate (PER) and bit error rate (BER), we search for the optimal scaling factor of the transfer function in the output layer of the MLP/BP neural networks and add small random disturbances to the training data. As compared with the conventional MLP/BP-based DFEs and the soft output MLP/BP-based DFEs, the proposed MLP/BP-based soft DFEs under multi-path fading channels can improve over 3-0.6 dB at PER=10-1 and over 3.3-0.8 dB at BER=10-3.

Silva and Krogh formulate a sampled-data hybrid automaton to deal with time-driven events and discuss its verification. In this paper, we consider a state feedback control problem of the automaton. First, we introduce two transition systems as semantics of the automaton. Next, using these transition systems, we derive necessary and sufficient conditions for a predicate to be control-invariant. Finally, we show that there always exists the supremal control-invariant subpredicate for any predicate.

This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.

This paper deals with the scattering of transverse magnetic (TM) plane wave by a perfectly conductive surface made up of a periodic array of finite number of rectangular grooves. By the modal expansion method, the total scattering cross section pc is numerically calculated for several different numbers of grooves. It is then found that, when the groove depth is less than wavelenght, the total scattering cross section pc increases linearly proportional to the corrugation width W. But an exception takes place at a low grazing angle of incidence, where pc is proportional to Wα and the exponent α is less than 1. From these facts, it is concluded that the total scattering cross section pc must diverge but pc/W the total scattering cross section per unit surface must vanish at a low grazing limit when the number of grooves goes to infinity.

This paper proposes a novel signal estimation method that uses a tensor product expansion. When a bivariable function, which is expressed by two-dimensional matrix, is subjected to conventional tensor product expansion, two single variable functions are calculated by minimizing the mean square error between the input vector and its outer product. A tensor product expansion is useful for feature extraction and signal compression, however, it is difficult to separate global noise from other signals. This paper shows that global noise, which is observed in almost all input signals, can be estimated by using a tensor product expansion where absolute error is used as the error function.

Antenna array is essential factor for multiple- input multiple-output (MIMO) wireless systems. Since the antenna array is composed of closely spaced elements, the mutual coupling among the elements cannot be ignored for the best performance of the array. Mutual coupling affects the MIMO channel, so the performance of a MIMO system, including channel capacity and diversity, varies with the degree of mutual coupling. The effect of mutual coupling is a function of the antenna load impedance. Therefore, designing an optimal element-matched array for a MIMO system requires consideration of the optimal matching condition for the array elements, the one that maximizes the channel capacity. We evaluated the effects of mutual coupling with various matching conditions in dipole arrays, and investigated their effects on the path correlation and channel capacity of MIMO systems. Simulation showed that the conventional conjugate matching of each element is still suitable for closely spaced elements except when the separation is about less than 0.1λ. Theoretical consideration of the received power of a closely-spaced-element array is also provided to show the effects of mutual coupling.

This paper presents two steganographic methods for JPEG2000 still images which approximately preserve histograms of discrete wavelet transform coefficients. Compared with a conventional JPEG2000 steganography, the two methods show better histogram preservation. The proposed methods are promising candidates for secure JPEG2000 steganography against histogram-based attack.

Recently, self-reconfigurable devices which can be partially reprogrammed by other part of the same device have been proposed. However, since conventional self-reconfigurable devices are LUT-array-based fine-grained devices, their time efficiency is spoiled by overhead for reconfiguration time to load large amount of configuration data. Therefore, we have to improve architectures. At the architecture design phase, it is difficult to estimate the performance, including reconfiguration overhead, of self-reconfigurable devices by static analysis, since it depends on many architecture parameters and unpredictable run-time behavior. In this paper, we propose a simulation-based platform for design exploration of self-reconfigurable devices. As a demonstration of the proposed platform, we implement an adaptive load distribution model on the devices of various reconfiguration granularities and evaluate performance of the devices.

We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2 Mb test device has been fabricated on 130 nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1 ns row-access time is achieved and 250 MHz operation can be realized by using 2 bank 8 b-burst mode.

A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 µW, respectively. The temperature coefficient of the reference voltage is 33 ppm/ at temperatures from -40 to 100. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 µm technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd=0.95-3.3 V).

A supply voltage (VDD) independent temperature sensor circuit, which can be realized by the optimum combination of three current modes of n-MOSFETs including the subthreshold current using the feedback scheme from the temperature dependent voltage (VTD) output to the gates of three n-MOSFETs, was proposed and fabricated by a standard 1.2 µm n-well CMOS process. The circuit consists of only 17 MOSFETs without high resistors resulting in a small die area of 0.18 mm2. The temperature coefficient TC of the sensor circuit can be controlled by the channel length ratio L4/L3 of two n-MOSFETs. The average temperature sensor voltage VTS and its typical TC are 1.77 V at VDD=5.0 V (20) and 5.1 mV/ for VDD=5.01.0 V in the temperature range of -20-100 in case of L4/L3=9, respectively.