We present a novel burst-mode transimpedance amplifier (TIA) with a gain-mode switching. The proposed TIA utilizes a regulated-cascode (RGC) input stage for broadband characteristics. To expand a dynamic range, the RGC controls a linear operating range depending on transimpedance gains by adjusting bias conditions. This TIA is implemented using the 0.18μm-CMOS technology. The experimental results show that the proposed TIA IC has a good eye-opening and can respond quickly to the burst data.

We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.

We numerically investigate a PDM-QPSK multi-rate coherent burst-mode optical receiver capable of receiving 3 different line-rates, suitable for next generation optical networks such as hybrid optical circuit switching (OCS)/optical packet switching (OPS) networks, access networks and datacenter networks. The line-rate detection algorithm relies on a simple-to-generate optical header, it is based on the fast Fourier transform (FFT) which can be efficiently implemented with the Goertzel algorithm, and it is insensitive to polarization rotations and frequency offset. Numerically, we demonstrate that performance in terms of packet detection rate (PER) can be tailored by controlling the sizes of the packet header and the line-rate estimator.

We report the adaptability of the burst-mode erbium-doped fiber amplifier (BM-EDFA) for uplink transmission of sharply rising analog radio-over-fiber (RoF) signals by using long-term evolution (LTE) -Advanced format on a mobile front-haul. Recent drastically increased mobile data traffic is boosting the demand for high-speed radio communication technologies for next-generation mobile services to enhance user experience. However, the latency become increasingly visible as serious issues. Analog RoF technology is a promising candidate for a next generation mobile front-haul to realize low latency. For the uplink, an RoF signal may rise sharply in response to a burst of in-coming radio signals. We propose that a newly developed BM-EDFA is applied for such a sharply rising RoF signal transmission. The BM-EDFA that we designed using enhanced intrinsic saturation power EDF to suppress the gain transient caused by received optical power fluctuations with optical feedback. The new BM-EDFA was designed for a wider linear output power range and lower NF than the previous BM-EDFA. The observed range of received optical power satisfying an error vector magnitude of less than 8%rms achieved over 16dB. We consider that our BM-EDFAs with wide linear ranges of output power will be a key device for the LTE-Advanced RoF uplink signal transmission via optical access networks for the next-generation mobile front-haul.

In this paper, we propose a flexible and high-capacity front-haul link for the uplink transmission of high-speed mobile signals using a cascade of radio-on-radio (RoR) and radio-over-fiber (RoF) systems. To emulate the cases that may occur in the uplink direction, we experimentally investigate the performance of superposing an uplink bursty LTE-A signal on the cascaded system using optical packet signal transmission. The performance of systems using different types of erbium-doped fiber amplifiers (EDFAs), including a high-transient EDFA, an automatic-gain-control EDFA, and a burst-mode (BM) EDFA is evaluated and compared. We confirm that the dynamic transience of the EDFAs has a significant influence on the signal performance. By using a BM-EDFA, we confirm successful transmission of the uplink packetized LTE-A signal on the cascaded system. Both the measured error vector magnitude and the received optical power range metrics exceed the requirements. We also estimate the maximum transmission range of the RoR link, and it is confirmed that a sufficiently long range could be achieved for the applications in mobile front-haul networks.

This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause data-transmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 µm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (<10-20).

Developing a rapid prototyping environment utilizing hardware description languages (HDLs) and conventional FPGAs can help ease and conquer the difficulties caused by the complexity of asynchronous digital systems and the advance of VLSI technology recently. We proposed a design flow and a FPGA template for implementing generalized C-element (gC) style asynchronous controllers. Utilizing conventional FPGA synthesis tools, self-timed bundled-data function modules can be realized with some effort on timing validation. The proposed design flow with FPGA-based realization approach is a very effective design methodology for rapid prototyping and functionality validation. This work could be useful for the early stage of performance estimation, power reduction exploration, circuits design training, and many other applications regarded asynchronous circuits. In this paper, the proposed FPGA-based asynchronous circuit design flow, a hands-on design tutorial, a generalized C-element template, and a list of synthesized benchmark circuits are documented and discussed in detail.

A 10-Gbit/s-class ac-coupled average-detection-type burst-mode receiver (B-Rx) with an ultra fast response and a high tolerance to the long consecutive identical digits has been developed. Key features of the circuit design are the baseline-wander common-mode rejection technique and the inverted distortion technique adopted in the limiting amplifier to cope with both the fast response and the high tolerance. Our B-Rx with newly developed limiting amplifier IC achieved a settling time of less than 150 ns, a sensitivity of -29.8 dBm, and a dynamic range of 23.8 dB with a 231-1 pseudo random bit sequences. Moreover, we also describe several potential B-Rx applications. We achieved better performance by applying the proposed systems to our B-Rx.

We describe a series of system measurements investigating the performance of a burst-mode or transient-suppressed (TS)-EDFA, specifically designed to reduce the impact of gain transients in dynamic optical networks. We assess the performance of this TS-EDFA in a variety of network contexts. We compare the performance of the TS-EDFA with conventional amplifiers (C-EDFAs) and show its compatibility with supplementary gain control techniques. Finally, we measure gain-transient accumulation along long links using a recirculating transmission loop and show that, for packet-transmission, the number of hops is limited by accumulated transients for a C-EDFA, but limited by accumulated noise for the TS-EDFA.

In this paper, we show the recent progress of photonic network technologies for the new generation network (NWGN). The NWGN is based on new design concepts that look beyond the next generation network (NGN) and the Internet. The NWGN will maintain the sustainability of our prosperous civilization and help resolve various social issues and problems by the use of information and communication technologies. In order to realize the NWGN, many novel technologies in the physical layer are required, in addition to technologies in the network control layer. Examples of cutting-edge physical layer technologies required to realize the NWGN include a terabit/s/port or greater ultra-wideband optical packet switching system, a modulation-format-free optical packet switching (OPS) node, a hybrid optoelectronic packet switching node, a packet-based reconfigurable optical add/drop multiplexer (ROADM) system, an optical packet and circuit integrated node system, and optical buffering technologies.

A hardware description languages (HDLs) based modeling technique for asynchronous circuits is presented in this paper. A HDLs handshake package has been developed for expressing handshake-style digital systems in both VHDL and Verilog. Burst-mode and extended burst-mode (BM/XBM) circuits were used to demonstrate the usefulness of this work. This research successfully prototyped comparators, adders, RSA encoder/decoder, and several self-timed circuits for the full-custom IC and FPGAs designs. Furthermore, the HDLs handshake package implemented by this research can be utilized to develop behavioral test benches for studying and analyzing asynchronous designs. Extracting detailed timing information from asynchronous finite state machines (AFSMs), detecting delay faults for synthesized self-timed functional modules, and locating fundamental mode violation within realized AFSMs are proven applications. The anticipated HDL modeling technique and the transformation procedure are detailed in the rest of this paper.

10G-EPON systems have attracted a great deal of attention as a way of exceeding to realize over 10 Gb/s for optical subscriber networking. Rapid burst-mode transmitting/receiving techniques are the key technologies enabling the burst-mode upstream transmission of 10G-EPON systems. In this paper, we have developed a OLT burst-mode 3R receiver incorporating a burst-mode AGC optical receiver and an 82.5 GS/s over-sampling burst-mode CDR and a ONU burst-mode transmitter with high launch power DFB-LD of 1.27 µm wavelength to fully compliant with IEEE802.3av 10G-EPON PR30 standards. The transmitting characteristics of a fast LD turn-on/off time of less than 6ns and a high launch power of more than +8.0 dBm, and the receiving characteristics of receiver sensitivity of -30.1 dBm and the upstream power budget of 38.1 dB are successfully achieved.

We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-µm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.

A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 µm CMOS process. Its active area is 0.41 mm2 and consumes 70 mW including I/O buffers from a 1.8 V supply.

In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.41.4 mm2, and power consumption is 32 mW under a 1.8-V supply voltage.

In this paper, a novel 622 Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35 µm CMOS process technology. Lock is accomplished on the first data transition and data are sampled at the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400-622 Mb/s burst mode input data without errors.

This paper presents an innovative 155Mb/s burst-mode laser transmitter chip, which was designed and successfully demonstrated, and contains several new subsystems: a digitally programmed current source, programmable up to 120mA with a resolution of 0.1mA, a fast but accurate intermittent optical level monitoring circuit, and a digital Automatic Power Control (APC) algorithm. This generic and intelligent chip was developed in a standard digital 0.35µm CMOS process. Extensive testing showed a high yield and algorithm stability, as well as excellent performance. During initialization, when the transmitter is connected to the Passive Optical Network (PON) for the first time, maximum three Laser Control Fields (LCF) are needed, with a length of 17bytes (0.88microsecond at 155Mb/s), to stabilize the laser output power. In this short time, the chip can regulate the launched optical output power of any FSAN (Full Service Access Network) compliant laser diode to the required level, even in the extreme circumstances caused by outdoor operation or by battery backup operation during power outages. Other tests show that the chip can further stabilize and track this launched optical power with a tolerance lower than 1dB over a wide temperature range, during the burst mode data transmission. The APC algorithm intermittently adjusts the optical power to be transmitted in a digital way, starting from loosely specified but safe preset values, to the required stable logic "1" and "0" level. No laborious calibration of the laser characteristic curve and storage of the calibration values in lookup tables are needed, nor any off-chip adjustable component. The power consumption is significantly reduced by disabling inactive circuitry and by gating the digital high-speed clock. Although this laser transmitter was developed for FSAN PON applications, which are standardized at a speed of 155Mb/s upstream, the design concept is quite generic and can be applied for developing a wide range of burst mode laser transmitters, such as required for Gigabit PON systems or other TDMA networks.

We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.

In modems for burst transmission of digital data, rapid carrier and clock synchronization are essential. Typically, frequency correction occurs prior to phase recovery since estimators are sensitive to frequency offsets. In this paper, we derive the bit error rate (BER) performance of a M-ary phase shift keying (MPSK) receiver in a closed form when there is no frequency offset estimator. Then we derive a relationship of the required burst length for certain BER with frequency offset estimator. To obtain the BER=10-4, approximately we need the burst length of 101 at Eb/N0=10 dB and 69 at Eb/N0=15 dB.

This paper describes a new timing circuit design technique for asynchronous burst-mode data transmission such as Fiber-To-The-Home (FTTH). It enables to the handling of asynchronous burst-mode data. Without an external reference clock signal, it can make a quick extraction of clock signal from received data packets using a "gating-timing circuit" and a "burst PLL." The gating-timing circuit employs bit gating for a quick phase response, and the burst PLL employs frame gating for quick frequency adjustment to differences between packets and clock extraction. This circuit has a simple configuration without any external oscillators, which reduces both cost and power. A fabricated 0.5-µm CMOS IC exhibits instantaneous response within one bit for 156 Mb/s asynchronous data packets.