This paper proposes a novel quad-band branched monopole antenna with a filter. The proposed antenna has a simple configuration in which branch-elements are added to a basic configuration consisting of a mast and dielectric wires. The antenna is characterized by performances such as wideband impedance matching, gain stabilization, and gain enhancement. Wideband impedance characteristics satisfying the voltage standing ratio of less than 2 are obtained by exciting a parallel resonance at the lowest band and multi-resonance at high bands. The filter suppressing higher order modes is used for gain stabilization, so that averaged gains above 5dBi are obtained at the quad-band. The antenna has a high gain of 11.1dBi because the branch-elements work as an end-fire array antenna at the highest band. Furthermore, it is clarified that an operating frequency is switched by using a variable bandpass filter at the lowest band. Last, a scale model of the antenna is fabricated and measured, then the effectiveness of the proposed antenna is demonstrated.

This study proposes a new structure of a single-shunt rectifier circuit that can reduce circuit loss and improve efficiency over the conventional structure. The proposed structure can provide impedance matching to the measurement system (or receiving antenna) without the use of conventional matching circuits, such as stubs and tapers. The proposed structure can simultaneously perform full-wave rectification and impedance matching by placing a feeding point on the output filter's λ/4 transmission line. We use circuit simulation to compare the RF-DC conversion efficiency and circuit loss of the conventional and proposed structures. The simulation results show that the proposed structure has lower circuit loss and higher RF-DC conversion efficiency than the conventional structure. We fabricate the proposed rectifier circuit using a GaAs Schottky barrier diode. The simulation and measurement results show that the single-shunt rectifier circuit's proposed structure is capable of rectification and impedance matching. The fabricated rectifier circuit's RF-DC conversion efficiency reaches a maximum of 91.0%. This RF-DC conversion efficiency is a world record for 920-MHz band rectifier circuits.

This paper presents a fully integrated yet compact receiver front-end for Sub-GHz applications such as Internet-of-Things (IoT). The low noise amplifier (LNA) matching network leverages an inductance boosting technique. A relatively small on-chip inductor with a compact area achieves impedance matching in such a low frequency. Moreover, a passive-mixer-first mode bypasses the LNA to extend the receiver dynamic-range. The passive mixer provides matching to the 50Ω antenna interface to eliminate the need for additional passive components. Therefore, the receiver can be fully-integrated without any off-chip matching components. The flipped-voltage-follower (FVF) cell is adopted in the low pass filter (LPF) and the variable gain amplifier (VGA) for its high linearity and low power consumption. Fabricated in 65nm LP CMOS process, the proposed receiver front-end occupies 0.37mm2 core area, with a tolerable input power ranging from -91.5dBm to -1dBm for 500kbps GMSK signal at 924MHz frequency. The power consumption is 1mW power under a 1.2V supply.

This paper theoretically presents that a terahertz (THz) oscillator using a resonant tunneling diode (RTD) and a rectangular cavity, which has previously been proposed, can radiate high output power by the impedance matching between RTD and load through metal-insulator-metal (MIM) capacitors. Based on an established equivalent-circuit model, an equation for output power has been deduced. By changing MIM capacitors, a matching point can be derived for various sizes of rectangular-cavity resonator. Simulation results show that high output power is possible by long cavity. For example, a high output power of 5 mW is expected at 1 THz.

This study proposes a design method for a rectifier circuit that can be rapidly charged by focusing on the design-load value of the circuit and the load fluctuation of a storage capacitor. The design-load value is suitable for rapidly charging the capacitor. It can be obtained at the lowest reflection condition and estimated according to the circuit design. This is a conventional method for designing the rectifier circuit using the optimum load. First, we designed rectifier circuits for the following three cases. The first circuit design uses a load set to 10 kΩ. The second design uses a load of 30 kΩ that is larger than the optimum load. The third design utilizes a load of 3 kΩ. Then, we measure the charging time to design the capacitor on each circuit. Consequently, the results show that the charge time could be shortened by employing the design-load value lower than that used in the conventional design. Finally, we discuss herein whether this design method can be applied regardless of the rectifier circuit topology.

A methodology for obtaining semi-custom high-power amplifiers (HPAs) is described. The semi-custom concept pertains to the notion that a selectable output power is attainable by replacing only transistors. To compensate for the mismatch loss, a new output matching network that can be easily tuned by wiring is proposed. Design equations were derived to determine the circuit parameters and specify the bandwidth limitations. To verify this methodology, a semi-custom HPA with GaN HEMTs was fabricated in the S-band. A selectable output power from 240 to 150 W was successfully achieved while maintaining a PAE of over 50% in a 19% relative bandwidth.

Impedance mismatching is a major obstacle hindering the application of DC power line communication (DC-PLC) due to the unpredictability of access impedance and random loads. Researchers and manufacturers typically estimate the power line impedance level and use a fixed single-winding coupler to carry out signal coupling, which does not achieve accurate impedance matching and leads to large signal attenuation and low reliability. In this paper, a lumped parameter power line communication model for DC-PLC is established in which the optimal receiver winding ratio is derived from equivalent circuits. A modifiable impedance matching coupler was designed to achieve dynamic impedance matching, and a series of simulations were run to analyze the relationship among optimal winding ratio, power line impedance and series loads. The performance of different winding ratio couplers under varied frequency and load impedance was also measured in a laboratory environment to find that adopting the modifiable impedance matching coupler is indeed a useful strategy for achieving adaptive impedance matching with maximum signal power transfer.

This paper presents a novel circuit for impedance matching to a load moving along a transmission line. This system is called FERMAT: Far-End Reactor MATching. The FERMAT consists of a power transmission line and a variable reactor at its far-end. The proposed system moves standing-wave antinodes to the position of the vehicle in motion. Therefore, the moving vehicle can be fed well at any position on the line. As a theoretical result, we derive adjustable matching conditions in FERMAT. We verified that the experimental result well agrees with the theory.

We propose a wideband antenna that has both vertical and horizontal polarization to create access points with enhanced connectivity. The antenna is composed of a rectangular plate and a ground plate, and the rectangular plate is fed sideways from the ground plate. Its -10dB fractional bandwidth is approximately 162%. It is shown that the offset feed of the rectangular plate is important to attain wideband impedance matching and vertical polarized wave. The results of a parametric study to characterize the first- and second-lowest resonant frequencies are presented. Moreover, the behavior of the impedance matching and polarization is interpreted by dividing the current distribution around the feed port on the rectangular plate into the same direction current mode and the opposite direction current mode. The measured results for the return loss and the radiation pattern of a prototype antenna agree well with the simulation results, therefore the wideband property was experimentally confirmed.

Internal power losses in lumped-element impedance matching circuits are formulated by means of Q factors of the elements and port impedances to be matched. Assuming that Q factors are relatively high, the above mentioned loss is expressed by a simple formula containing only the tangents of the impedances. The formula is a powerful tool for such applications that put emphasis on power efficiency as wireless power transfer. As well as the formulation, we illustrate some design examples with the derived formula: design of the least lossy L-section circuit and two-stage low-pass ladder. The examples provide ready-to-use knowledge for low-loss matching design.

Near field communication (NFC) antennas are often lined with magnetic sheets to reduce performance degradation caused by nearby metal objects. Though amorphous sheets have a high permeability and are suitable magnetic sheets for lining, their magnetic loss is also high. Therefore, this paper suggests a technique of suppressing magnetic loss by modifying the shape of the sheet without changing its composition. The utility of the proposed technique was investigated in this study.

Wireless power transfer (WPT) based on electric coupled resonance can withstand a great level of variability in antenna separation. In this paper, we propose an independent electrical coupled resonance WPT system to further increase such systems' power transfer distance and ensure flexibility in the antenna location. The proposed system's power transfer function, critical coupling point, and resonance frequency splitting are investigated via the equivalent circuit, simulation, and experiment. Moreover, the input impedance characteristic of two electric coupled resonance antennas is also analyzed according to the transfer distance. In the region of under coupled, an appropriate impedance matching method is required to achieve effective power transfers. Here, we proposed a fixed configuration type matching loop with a series-connecting variable capacitance that can be added into both the source and load antennas. Experimental results demonstrate that the proposed matching loop can convert the two electric coupled resonance antennas' input impedance to the feed port impedance very well at varying transfer distances; these results are in good agreement with the simulation results.

By using impedance (Z) matching circuits in a low-cost transistor outline (TO) CAN package for a 10 Gb/s transmitter, we achieve a cost-effective and small bidirectional optical subassembly (BOSA) with excellent optical transmission waveforms and a > 40% mask margin over a wide temperature range (-10 to 85). We describe a design for Z matching circuits and simulation results, and discuss the advantage of the cost-effective compensation technique.

In this paper, effects of the parasite elements on an antenna impedance of a UHF RFID tag put on a high impedance surface (HIS) are experimentally studied in detail. It is shown that small parasite elements on a mushroom HIS structure can help to recover a mismatch of the impedance and this impedance recovery is brought by an in-phase frequency shift of the HIS due to a mutual coupling between the HIS and the parasite elements. The technique is applied to a commercial 953 MHz band RFID tag inlet antenna on a 53-cell HIS with the total dimension of 125751.5 mm3 and it is demonstrated that the impedance mismatch is successfully recovered and the tag operates with a reading range of 3 m even on a 2003002 mm3 aluminum plate.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.

A monolithic modulator driver IC based on InP HBTs with a new circuit topology -- called a functional distributed circuit (FDC) -- for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2:1 multiplexing function produces 2.6-Vp-p (differential output: 5.2 Vp-p) and 2.4- Vp-p (differential output: 4.8 Vp-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80 Gb/s and 90 Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO3 Mach-Zehnder modulator up to 90 Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.

The characteristics of two-stage composite right- and left-handed (CRLH) transmission lines are discussed. The dispersion relationship of both balanced and unbalanced two-stage CRLH lines is described, together with numerical calculations that demonstrate their potential.

Three dimensional (3D) integrated circuits (ICs) have the potential to significantly enhance VLSI chip performance, functionality and device packing density. Interconnects delay and signal integrity issues are critical in chip design. In this paper, we extend the idea of redundant via insertion of conventional 2D ICs and propose an approach for vias insertion/placement in 3D ICs to minimize the propagation delay of interconnects with the consideration of signal integrity. The simulation results based on a 65 nm CMOS technology demonstrate that our approach in general can result in a 9% improvement in average delay and a 26% decrease in reflection coefficient. It is also shown that the proposed approach can be more effective for interconnects delay improvement when it is integrated with the buffer insertion in 3D ICs.

Application of microwave and millimeter-wave circuit technologies to InGaP-HBT ICs for 40-Gbps optical-transmission systems is demonstrated from two aspects. First, ICs for various important functions -- amplification of data signals, amplification, frequency doubling, and phase control of clock signals -- are successfully developed based on microwave and millimeter-wave circuit configurations mainly composed of distributed elements. A distributed amplifier exhibits ≥164-GHz gain-bandwidth product with low power consumption (PC) of 71.2 mW. A 20/40-GHz-band frequency doubler achieves wideband performance (40%) with low PC (26 mW) by integrating a high-pass filter and a buffer amplifier (as a low-pass filter). A compact 40-GHz analog phase shifter, 20- and 40-GHz-band clock amplifiers with low PC are also realized. Second, a familiar concept in microwave-circuit design is applied to a high-speed digital circuit. A new approach -- inserting impedance-transformer circuits -- to enable 'impedance matching' in digital ICs is successfully applied to a 40-Gbps decision circuit to prevent unwanted gain peaking and jitter increase caused by transmission lines without sacrificing chip size.