We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.

We attempt to design and fabricate of a 4×4 Butler matrix for short-millimeter-wave frequencies by using the microfabrication process for a polytetrafluoroethylene (PTFE) substrate-integrated waveguide (SIW) by the synchrotron radiation (SR) direct etching of PTFE and the addition of a metal film by sputter deposition. First, the dimensions of the PTFE SIW using rectangular through-holes for G-band (140-220 GHz) operation are determined, and a cruciform 90 ° hybrid coupler and an intersection circuit are connected by the PTFE SIW to design the Butler matrix. Then, a trial fabrication is performed. Finally, the validity of the design result and the fabrication process is verified by measuring the radiation pattern.

In flat panel display (FPD) lithography, a high resolution and large depth of focus (DOF) are required. The demands for high throughput have necessitated the use of large glass plates and exposure areas, thereby increasing focal unevenness and reducing process latitude. Thus, a large DOF is needed, particularly for high-resolution lithography. To manufacture future high-definition displays, 1.0μm line and space (L/S) is predicted to be required, and a technique to achieve this resolution with adequate DOF is necessary. To improve the resolution and DOF, resolution enhancement techniques (RETs) have been introduced. RETs such as off-axis illumination (OAI) and phase-shift masks (PSMs) have been widely used in semiconductor lithography, which utilizes narrowband illumination. To effectively use RETs in FPD lithography, modification for broadband illumination is required because FPD lithography utilizes such illumination as exposure light. However, thus far, RETs for broadband illumination have not been studied. This study aimed to develop techniques to achieve 1.0μm L/S resolution with an acceptable DOF. To this end, this paper proposes a method that combines our previously developed RET, namely, divided spectrum illumination (DSI), with an attenuated PSM (Att. PSM). Theoretical observations and simulations present the design of a PSM for broadband illumination. The transmittance and phase shift, whose degree varies according to the wavelength, are determined in terms of aerial image contrast and resist loss. The design of DSI for an Att. PSM is also discussed considering image contrast, DOF, and illumination intensity. Finally, the exposure results of 1.0μm L/S using DSI and PSM techniques are shown, demonstrating that a PSM greatly improves the resist profile, and DSI enhances the DOF by approximately 30% compared to conventional OAI. Thus, DSI and PSMs can be used in practical applications for achieving 1.0μm L/S with sufficient DOF.

The microfabrication technique based on synchrotron radiation (SR) direct etching process has recently been applied to construct PTFE microstructures. This paper proposes a PTFE substrate integrated waveguide (PTFE SIW). It is expected that the PTFE SIW contributes to the improvement of the structural strength. A rectangular through-hole is introduced taking the advantage of the SR direct etching process. First, a PTFE SIW for the Q-band is designed. Then, a cruciform 3-dB directional coupler consisting of the PTFE SIW is designed and fabricated by the SR direct etching process. The validity of the PTFE SIW coupler is confirmed by measuring the frequency characteristics of the S-parameters. The mechanical strength of the PTFE SIW and the peeling strength of its Au film are also additionally investigated.

The microfabrication technique based on SR (Synchrotron Radiation) direct etching process has recently been applied to construct PTFE microstructures. This paper attempts to fabricate an integrated PTFE-filled waveguide Butler matrix for short millimeter-wave by SR direct etching. First, a cruciform 3-dB directional coupler and an intersection circuit (0-dB coupler) are designed at 180 GHz. Then, a 4×4 Butler matrix with horn antennas is designed and fabricated. Finally, the measured radiation patterns of the Butler matrix are shown.

Novel roll-to-roll (R2R) deposition and patterning of ITO on ultra-thin glass were developed with no photolithography and applied to flexible organic light emitting diodes (OLEDs). The developed deposition consists of low temperature sputtering and annealing. The developed patterning utilizes an etching paste printed by novel R2R screen printing.

For the future medical diagnostics, high-sensitive, rapid, and cost effective biosensors to detect the biomarkers have been desired. In this study, the polymer-based two-dimensional photonic crystal (2D-PC) was fabricated using nanoimprint lithography (NIL) for biosensing application. In addition, for biosensing application, label-free detection of fibrinogen which is a biomarker to diagnose the chronic obstructive pulmonary disease (COPD) could be achieved using antigen-antibody reaction high-sensitively (detection limit: pg/ml order) and rapidly. Using this polymer-based 2D-PC, optical biosensor can be developed cost effectively. Furthermore, by using polymer as a base material for fabrication of 2D-PC, label-free detection of antigen-antibody reaction can be performed in visible region.

The individual steps of UV imprint lithography have been explained in detail from the points of manufacturing nano-structures. The applications to photonic devices have been also introduced.

We investigated optical transmission characteristics of aluminum thin films with periodic hole arrays in sub-wavelength. We divided white light into several color spectra using a color filter based on the surface plasmon resonance (SPR) utilizing aluminum showing high plasma frequency. By optimizing a hole-array period, hole shape, polarization and index difference of two surface, transmittance of 30% and full-width at half-maximum of around 100 nm were achieved.

The metallic waveguide is one of many effective media for millimeter- and submillimeter-waves because of the advantage of its low-loss nature. This paper describes the fabrication method of PTFE-filled waveguide components with the use of the SR (synchrotron radiation) direct etching process of PTFE, sputter deposition of metal, and electroplating. PTFE is known as a difficult material to process with high precision. However, it has been reported that PTFE microstructures can be fabricated by the direct exposure to SR. First, an iris-coupled waveguide BPF with 5-stage Chebyshev response is designed and fabricated for the Q-band. It is demonstrated that the present process is applicable for the fabrication of the practical components inclusive of narrow patterns. Then, a cruciform 3 dB coupler with air-filled posts is designed and fabricated for the Q-band. Directivity and matched state of the coupler can be realized by “holes” in the dielectric material. The measurement results are also shown.

We report a new approach to creating a 'solid ink' and direct patterning of InAs nanowires on a Si substrate using dip-pen nanolithography (DPN). The normal method to prepare an 'ink' is a solution-based process using sonication to liquidize nanoparticles, which we call 'liquid ink' in this paper. As ink-solution-based DPN patterning has been prevalent in most studies, herein we propose a new method, 'solid inking', by which the inking process is solution-free. In our work, InAs nanowires were transferred to an AFM tip by directly scanning the tip over an InAs nanowire wafer at humidity over 80%. By this method, the preparation of ink and the 'inking' process is combined into one step, and a large amount of nanowires can be collected onto the tip to ensure the formation of a continuous ink flow for the direct patterning.

We propose a character size optimization technique to reduce the number of EB shots of multi-column-cell (MCC) lithographic systems in which transistor patterns are projected with multiple column cells in parallel. Each and every column cell is capable of projecting patterns with character projection (CP) and variable shaped beam (VSB) methods. Seeking the optimal character size of characters contributes to minimizing the number of EB shots and reducing the fabrication cost for ICs. Experimental results show that the character size optimization achieved 70.6% less EB shots in the best case with an available electron beam (EB) size. Our technique also achieved 40.6% less EB shots in the best case than a conventional character sizing technique.

Character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask manufacture because it can project ICs much faster than point beam projection or variable-shaped beam (VSB) projection. In this paper, we first present a projection mask set development methodology for multi-column-cell (MCC) systems, in which column-cells can project patterns in parallel with the CP and VSB lithographies. Next, we present an INLP (integer nonlinear programming) model as well as an ILP (integer linear programming) model for optimizing a CP mask set of an MCC projection system so that projection time is reduced. The experimental results show that our optimization has achieved 33.4% less projection time in the best case than a naive CP mask development approach. The experimental results indicate that our CP mask set optimization method has virtually increased cell pattern objects on CP masks and has decreased VSB projection so that it has achieved higher projection throughput than just parallelizing two column-cells with conventional CP masks.

Organic static induction transistor (OSIT) is a promising driving device for the displays, since it shows high-speed, high-power and low-voltage operation. In this study, the OSIT with fine gate electrode patterned by electron beam exposure were fabricated. We investigated the basic electrical characteristics of copper phthalocyanine OSIT and compared with the calculation results obtained by two-dimensional (2D) device simulator. The experimental results show that the gate modulation improved by reducing the electrode gap and on/off current ratio depends on the gate gap.

An ultra-deep polymer cavity structure exposed using deep X-ray lithography is used as a template for metal electroforming to produce a 24-GHz cavity resonator. The metal cavity is 1.8 mm deep and has impressive structure, including extremely vertical and smooth sidewalls, resulting in low conductor loss. The measured resonator has an unloaded quality factor of above 1800 at a resonant frequency of 23.89 GHz.

The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and leads to a price rise of IC devices. This paper discusses a technology mapping technique for enhancing the throughput of the CP lithography. The number of electron beam (EB) shots to project an entire chip directly determines the fabrication time for the chip as well as the throughput of CP equipment. Our technology mapping technique maps EB shot count-effective cells to a circuit in order to increase the throughput of CP equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with a conventional technology mapping, our technology mapping technique has achieved 26.6% reduction of the number of EB shots for the front-end-of-the-line (FEOL) process without any performance degradation of ICs. Moreover, our technology mapping technique has achieved a 54.6% less number of EB shots under no performance constraints. It is easy for both IC designers and equipment developers to adopt our technique because our technique is a software approach with no additional modification on CP equipment.

A well-defined test structure of organic static-induction transistor (SIT) having regularly sized nano-apertures in the gate electrode has been fabricated by colloidal lithography using 130-nm-diameter polystyrene spheres as shadow masks during vacuum deposition. Transistor characteristics of individual nano-apertures, namely 'nano-SIT,' have been measured using a conductive atomic-force-microscope (AFM) probe as a movable source electrode. Position of the source electrode is found to be more important to increase current on/off ratio than the distance between source and gate electrodes. Experimentally obtained maximum on/off ratio was 710 (at VDS = -4 V, VGS = 0 and 2 V) when a source electrode was fixed at the edge of gate aperture. The characteristics have been then analyzed using semiconductor device simulation by employing a strongly non-linear carrier mobility model in the CuPc layer. From device simulation, source current is found to be modulated not only by a saddle point potential in the gate aperture area but also by a pinch-off effect near the source electrode. According to the obtained results, a modified structure of organic SIT and an adequate acceptor concentration is proposed. On/off ratio of the modified organic SIT is expected to be 100 times larger than that of a conventional one.

The feasibility of a new transistor structure was demonstrated through an experimental observation of current gain and voltage gain. The proposed transistor structure is a hot electron transistor without a base layer to minimize scattering. Electron emission from the emitter is controlled using positively biased Schottky gate electrodes located on both sides of the emitter mesa. Monte Carlo simulation shows an estimated delay time of 0.17 ps and low gate leakage current with open-circuit voltage gain over unity. To confirm the basic operation, the device with a 25 nm wide emitter was fabricated. To obtain saturated current-voltage characteristics, the emitter was surrounded by gates and parasitic regions were eliminated by electron beam lithography. The observed open-circuit voltage gain was 25. To obtain a low leakage current, an electron energy smaller than the Γ-L separation was necessary to maintain the ballistic nature of the electron. When the gate-emitter voltage was 0.8 V, the gate leakage current was only 4% of the collector current. Thus voltage amplication and current amplification were confirmed simultaneously.

The lithography process on the deep trench pattern above the large cavity is proposed to fabricate the MEMS structure. Generally, bubbles generated on the trench patterns when it was baked after coating resist. The probability of the generation of bubbles was reduced by decreasing the backing rate. The fast scanning micromirror with 50.8 kHz resonant frequency was fabricated by controlling the backing rate.

The non-linear quasiparticle tunnel current flowing in a distributed superconductor-insulator-superconductor (SIS) transmission line resonator has been exploited in a low-noise heterodyne fixed-tuned waveguide receiver in the 600-700 GHz band. The mixer employs two half-wave or full-wave distributed SIS long junctions connected in series. These devices have been fabricated with optical lithography. At 654 GHz, a Y-factor of 1.79 has been recorded, corresponding to a double-side-band (DSB) receiver noise temperature of 198 K at an IF of 3 GHz.