We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.

Asymmetrically designed polycrystalline silicon (poly-Si) thin film transistors (TFT) were fabricated and investigated to suppress kink effect and to improve electrical reliability. Asymmetric dual channel length poly-Si TFT (ADCL) shows the best reduction of kink and leakage currents. Technology computer-aided design simulation proves that ADCL can induce properly high voltage at floating node of the TFT at high drain-source voltage (VDS), which can mitigate the impact ionization and the degradation of the transconductance of the TFT showing high reliability under the hot carrier stress.

Enhancing the performance of low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) requires high-quality poly-Si films. One of the authors (A.H.) has already demonstrated a continuous-wave (CW) laser lateral crystallization (CLC) method to improve the crystalline quality of thin poly-Si films, using a diode-pumped solid-state CW laser. Another candidate method to increase the on-current and decrease the subthreshold swing (s.s.) is the use of a high-k gate stack. In this paper, we discuss the performance of top-gate CLC LT poly-Si TFTs with sputtering metal/hafnium oxide (HfO2) gate stacks on nonalkaline glass substrates. A mobility of 180 cm2/Vs is obtained for n-ch TFTs, which is considerably higher than those of previously reported n-ch LT poly-Si TFTs with high-k gate stacks; it is, however, lower than the one obtained with a plasma enhanced chemical vapor deposited SiO2 gate stack. For p-ch TFTs, a mobility of 92 cm2/Vs and an s.s. of 98 mV/dec were obtained. This s.s. value is smaller than the ones of the previously reported p-ch LT poly-Si TFTs with high-k gate stacks. The evaluation of a fabricated complementary metal-oxide-semiconductor inverter showed a switching threshold voltage of 0.8 V and a gain of 38 at an input voltage of 2.0 V; moreover, full swing inverter operation was successfully confirmed at the low input voltage of 1.0 V. This shows the feasibility of CLC LT poly-Si TFTs with a sputtered HfO2 gate dielectric on nonalkaline glass substrates.

Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below $550^{circ}$C, to realize high performance and low power dissipation system-on-glass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substrate and the TG was fabricated by a self-alignment process using the BG as a photomask. This structure is called embedded metal double-gate (E-MeDG) in this paper. The poly-Si channel with lateral large grains was fabricated using a continuous-wave laser lateral crystallization (CLC). The self-aligned 4T E-MeDG LT poly-Si TFT, with a gate length of 5,$mu $m and TG and BG SiO$_2$ thicknesses of 50 and 100,nm, respectively, exhibited a subthreshold swing of 120,mV/dec and a threshold voltage ($mathrm{V}_{mathrm{th}}$) of $-$0.5,V in the connecting DG mode; i.e. when TG is connected to BG. In the TG operation at various BG control voltage, a threshold voltage modulation factor $(gamma = Delta mathrm{V}_{mathrm{th}}/Delta mathrm{V}_{mathrm{BG}})$ of 0.47 at negative BG control voltage and 0.60 at positive BG control voltage are demonstrated, which values are nearly equal to theoretical prediction of 0.40 and 0.75. Trend of subthreshold swing (s.s.) of TG operation under different BG control voltage are also consistent with theoretical prediction. In addition to TG operation, successful BG operation under various TG control voltages was confirmed. Field-effect mobility derived from g$_{mathrm{m}}$ also varied depending on control gate voltage. The high controllability of device parameter of individual LT poly-Si TFTs is caused by excellent crystalline quality of CLC poly-Si film and will enable us to the fabrication of high-speed and low power-dissipation SoG.

We propose a temperature sensor employing a ring oscillator composed of poly-Si thin-film transistors (TFTs). Particularly in this research, we compare temperature sensors using TFTs with lightly-doped drain structure (LDD TFTs) and TFTs with offset drain structure (offset TFTs). First, temperature dependences of transistor characteristics are compared between the LDD and offset TFTs. It is confirmed that the offset TFTs have larger temperature dependence of the on current. Next, temperature dependences of oscillation frequencies are compared between ring oscillators using the LDD and offset TFTs. It is clarified that the ring oscillator using the offset TFTs is suitable to detect the temperature. We think that this kind of temperature sensor is available as a digital device.

A multigate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) is a recently popular topic in the field of Si devices. In this study, self-aligned planar metal double-gate poly-Si TFTs consisting of an embedded bottom metal gate, a top metal gate fabricated by a self-alignment process, and a lateral poly-Si film with a grain size greater than 2 µm were fabricated on a glass substrate at 550. The nominal field-effect mobility of an n-channel TFT is 530 cm2/Vs, and its subthreshold slope is 140 mV/dec. The performance of the proposed TFTs is superior to that of top-gate TFTs fabricated using equivalent processes.

In this paper, we compare 1/f noise characteristics of High-k/Metal Gate MOSFET and SiON/Poly-Si Gate MOSFET experimentally, and evaluate the time fluctuation of drive current. These MOSFETs are fabricated with 65 nm CMOS process, and their gate lengths (Lg) are 130 nm. Specifically, we focus on the dependency of the time fluctuation of drive current on channel width (W) and temperature (T). First, we evaluate the dependency on channel width. In the case of SiON/Poly-Si Gate MOSFET, when the channel width is narrow such as W=200 nm and W=250 nm, Power Spectrum Density (PSD) depends on 1/f2 at two frequency regions. Moreover, as the channel width is wide such as W=300 nm, W=500 nm and W=1000 nm, PSD depends on 1/f and the value of PSD shifts lower. This is a new phenomena observed for the first time. On the other hand, in the case of High-k/Metal Gate MOSFET, the value of PSD is about 100 times larger than that of SiON/Poly-Si Gate MOSFET. Moreover, there is no dependency of PSD on channel width ranges from 150 nm to 1000 nm. Second, we evaluate the dependency on temperature. In the case of SiON/Poly-Si Gate MOSFET, when the temperature (T) is lowered from T=27 to T=-35, the dependency changes from the 1/f dependency to the 1/f2 dependency at two different frequency regions. This is also a new phenomena observed for the first time. However, in the case of High-k/Metal Gate MOSFET, there is no dependency of PSD on temperature ranges from 27 to -35. These results are useful knowledge for designing future LSI, because PSD dependency shows different characteristics when both channel width and temperature are changed.

The electrical properties of poly-Si thin film transistors (TFTs) using rapid thermal annealing with various gate oxide thicknesses were studied in this work. It was found that Poly-Si TFT electrical characteristics with the thinnest gate oxide thickness after RTA treatment exhibits the largest performance improvement compared to TFT with thick oxide as a result of the increased incorporated amounts of the nitrogen and oxygen. Thus, the combined effects can maintain the advantages and avoid the disadvantages of scaled-down oxide, which is suitable for small-to-medium display mass production.

The polycrystalline silicon (poly-Si) TFT has two insulator interfaces between the polycrystalline silicon and front and back insulators. These interfaces have trap states, which affect the characteristics of poly-Si TFT. In the silicon-on-insulator (SOI) technology area, using the dual-gated, fully-depleted SOI MOSFET under the depleted back-channel condition, the back-interface trap density can be calculated through the front-channel threshold voltage and film thicknesses. The front-interface trap density is also evaluated changing the roles of both gates. This evaluation method for front- and back- interface trap densities is called the threshold-voltage method. To apply this threshold-voltage method to the "medium-thickness" poly-Si TFT, of which the channel is not fully depleted in normal single gate bias operation, the biases for both front and back gates are controlled to realize full depletion. Under the fully-depleted condition, the front- or back- threshold voltage of poly-Si TFT is carefully extracted by the second-derivative method changing back- and front- gate biases. We evaluated the front- and back- interface trap densities not only for normal operation but also under stress. To evaluate the bias and temperature stress effect, we used two types of samples, which are made by different processes. The evaluated front- and back- interface trap densities for both samples in initial state are around 51011 to 1.31012 cm-2eV-1, which are almost the same as the reported values. Applying bias and temperature stress shows the variation of these interface-trap densities. Samples with large shifts of the front-channel threshold voltage show large trap density variation. On the other hand, samples with small threshold voltage shifts show small trap density variation. The variation of the back-interface trap density during the stress application showed a correlation to the front-channel threshold voltage shift.

A two-dimensional (2-D) physical model of n-channel poly-Si LDD TFTs in comparison with that of SD TFTs is presented to analyze hot-carrier degradation. The model is based on 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. We have shown that, in the current saturation bias (Vg

Poly-Si TFT (Thin Film transistor) fabricated below 170 using excimer laser crystallization of sputtered Si films was characterized. In particular, a gate insulator with a breakdown field exceeding 8 MV/cm was deposited by using ICP (Inductively Coupled Plasma) CVD (Chemical Vapor Deposition). A buffer layer possessing high thermal conductivity was inserted between the active channel and the plastic substrate, in order to protect the plastic substrate from the thermal energy of the laser and to increase adhesion of Si film on plastic. Using this method, we successfully fabricate TFT with a stable electron field-effect mobility value greater than 14.7 cm2/Vsec.

The role of electric field in metal-induced lateral crystallization (MILC) of amorphous Si (a-Si) under limited Ni-supply condition has been investigated. The nominal lateral-growth rate was increased from 3.6 µm/h (no-electric field) to 23 µm/h at the positive electrode side and reduced to 2.8 µm/h at the negative electrode side in presence of the electric field of 20 V/cm. However, spontaneously nucleated needle-like Si crystals were observed in the enhanced positive electrode side, which have been found to be independent of the MILC. Further investigation under the condition where Ni in the supply region was removed on the way of crystallization revealed that the electric field enhanced crystallization greatly reduced. These results indicate that the electric field does not enhance the MILC growth but enhances the diffusion of Ni in a-Si which takes place prior to the MILC growth.

We report, in this paper, on a combined process of photo-oxidation and PECVD using TEOS and O2 gases to produce an SiO2 gate insulator for poly-Si TFTs. Light of 172 nm-wavelength from a Xe excimer lamp generates active oxygen radicals efficiently and selectively without producing ozone. These oxygen radicals efficiently oxidize silicon. In contrast to plasma oxidation, photo-oxidation offers the ability to produce gate oxides without ion bombardment. Oxide-silicon interfaces with interface trap densities of 2-3 1010 cm-2 eV-1 were obtained by photo-oxidation at 200-300. A stack structure was produced using 4.3-nm-thick photo-oxide topped with a 40-nm-thick PECVD oxide film deposited at 300. This stack structure without annealing exhibited excellent interface behavior and the same J-E characteristics as a 100-nm-thick PECVD film annealed at 600.

We have successfully produced laterally-grown grains on large (300 350 mm) glass substrates by means of a newly developed excimer laser crystallization system that features a high-precision mask stage and an auto-focusing system. The original grains were produced with a steep beam edge and their lateral growth was extended by repeated irradiation and translation. TFTs fabricated with these extended grains were found to have mobilities that remained almost constant at 270 cm2/Vs (n-ch. TFTs) and 230 cm2/Vs (p-ch. TFTs) over a wide range of laser fluence (400-600 mJ/cm2).

Low-temperature poly-Si thin film transistor with gate-overlapped LDD (GOLD) structure was fabricated. Reliability was evaluated using electrical stress method comparing conventional LDD and single drain structures. As previous researchers have reported, we have confirmed that the degradation of ON current and the field effect mobility was very small compared to conventional LDD or non-LDD structures. We have analyzed the reliability of the GOLD TFT using two-dimensional device simulator. We have clarified that vertical negative field plays a dominant role for improving the reliability in the GOLD TFT. Impact ionization occurs far from the interface between the oxide and poly-silicon by the vertical negative field. GOLD structure is promising for the realization of system on panel.

A practical method of measuring the contact resistance of a phosphorus-doped poly-Si plug formed on a lightly phosphorus-doped diffusion region in DRAM memory cells is described. Contact resistance was obtained electrically, using ordinary contact-chain test structures, by changing the measurement of the substrate bias. This separated the bias-dependent resistance of the lightly doped diffusion layer from the total resistance. The method was used experimentally to evaluate the feasibility of forming low-resistance contacts down to a diameter of 130 nm for giga-bit DRAMs. Electrical measurement showed that reducing the interface resistance between the poly-Si plug and the lightly doped diffusion layer was effective for forming low-resistance contacts, though a specific interface layer could not be detected by TEM observation.

We have proposed and fabricated a new poly-Si TFT employing the selectively doped regions in the active layer. In the proposed poly-Si TFTs, the selectively doped regions where doping concentration is identical to that of the source/drain, reduce the effective channel length during the on-state. Under the off-state, the selectively doped regions may reduce the lateral electric field induced near the drain and reduce the leakage current considerably. The experimental data of the proposed TFT exhibit high on-current, low leakage current and low threshold voltage. The fabrication of the proposed TFT is rather simple; the required steps for the proposed TFT are reduced because high dosage ion-implantation for the source/drain and the selectively doped regions is performed simultaneously prior to excimer laser irradiation step.

Pb(ZrxTi1-x)O3 (PZT) thin films were prepared on various electrodes. When Ir system materials were used as electrodes, fatigue properties of PZT thin films were improved. Moreover, in the case of the PZT thin film on an Ir/IrO2 electrode, not only fatigue but imprint properties were clearly improved. We could find these improvements were caused by good barrier effect of IrO2 from secondary ion mass spectroscopy (SIMS) analysis. By applying these Ir system electrodes, we fabricated stacked capacitors on polycrystalline silicon (poly-Si) plugs. In spite of high temperature thermal processing, we found poly-Si plugs were ohmically connected with the bottom electrodes of the capacitors from hysteresis measurements and I-V characteristics, and could greatly expect them for practical use.

We have studied in detail the effect of gas flow rates on the film properties of low-temperature (300) polycrystalline silicon (poly-Si) films prepared by conventional plasma enhanced chemical vapor deposition (13.56 MHz) with SiF4/SiH4/H2 gases. The effect of SiH4 flow rate on crystallization is shown to be large. A small amount of SiH4 with high SiF4 and H2 flow rates (50[H2]/[SiH4]1200, 20[SiF4]/[SiH4]150, 1[H2]/[SiF4]16) is important to form poly-Si films. The poly-Si films deposited under such optimized conditions had shown preferential 〈110〉-orientation and the crystalline fraction is estimated to be more than 80%. The deposition rates are in the range of 5-30 nm/min. The conductivity is in the range of 10-8-10-6 S/cm. Further, the electrical conduction indicates an activation type, and the activation energy is in the range of 0.5-0.6 eV.

A simulation model for arsenic diffusion in polycrystalline silicon has been developed considering dynamic dopant clustering and polysilicon grain growth kinetics tightly coupled with dopant diffusion and segregation. It was assumed that the polysilicon layer consists of column-like grains surrounded by thin grain-boundaries, so that one dimensional description is permissible for dopant diffusion. The dynamic clustering model was introduced for describing arsenic activation in polysilicon grains, considering the solubility limit increase for arsenic in a polysilicon. For a grain-growth calculation, a previous formula was modified to include a local concentration dependence. The simulation results show that these effects are significant for a high dose implantation case.