We have fabricated VDP (van der Pauw) stress sensors on (111) silicon surfaces. This work focuses on a study of strain effects in VDP stress sensors, which were generally ignored in previous works, for the precise measurements of die stresses in electronic packages. The stress sensitivity was observed to be approximately 10% larger for p-type VDP sensors compared to n-type VDP sensors.

In this paper, it is shown that our fabricated MTJ of 60180 nm2, which is connected to the MOSFET in series by 3 levels via and 3 levels metal line, can dynamically operate with the programming current driven by 0.14 µm CMOSFET. In our measurement of transient characteristic of fabricated MTJ, the pulse current, which is generated by the MOSFET with an applied pulse voltage of 1.5 V to its gate, injected to the fabricated MTJ connected to the MOSFET in series. By using the current measurement technique flowing in MTJ with sampling period of 10 nsec, for the first time, we succeeded in monitor that the transition speed of the resistance change of 60180 nm2 MTJ is less than 30 ns with its programming current of 500 µA and the resistance change of 1.2 kΩ.

In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/ 1-poly Gate 0.14 µm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60180 nm2 achieves a large change in resistance of 3.52 kΩ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320 µA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.

Electrical contacts are an important part of electrical circuits and many reliability problems are related to electrical contact failure. It is important to investigate the relationship between load and contact resistance which is an important factor of contact reliability. In this study, the effect of plated material and plated thickness on contact resistance was examined. The samples were constructed of a copper alloy with tin or silver plating. Contact configuration was hemispherical-flat contact. The contact resistance was measured by using a four-probe method with a load up to 40 N. The relation between indentation contact area (i.e. apparent contact area) and contact resistance was determined. As experimental results, the contact resistance depends on the indentation of the contact area. In the same contact area, tin-plated samples have higher resistance than those that are silver-plated due to their own resistivity. The constriction resistance of a plated layer, which depends on contact area, plated material and plated thickness, is analyzed by a theoretical solution, which is shown by R=Φρ /2a, using a surface resistance coefficient Φ . The theoretical results show almost good agreement with the experimental results. Thus, the indentation contact area (i.e. apparent contact area) is almost the same as the real contact area in this study.

A multiple-peak negative differential resistance (NDR) circuit made of standard Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) is demonstrated. We can obtain a three-peak I-V curve by connecting three cascoded MOS-HBT-NDR circuits by suitably designing the MOS parameters. This novel three-peak NDR circuit possesses the adjustable current-voltage characteristics and high peak-to-valley current ratio (PVCR). We can adjust the PVCR values to be as high as 11.5, 6.5, and 10.3 for three peaks, respectively. Because the NDR circuit is a very strong nonlinear element, we discuss the extrinsic hysteresis phenomena in this multiple-peak NDR circuit. The effect of series resistance on hysteresis phenomena is also investigated. Our design and fabrication of the NDR circuit is based on the standard 0.35 µm SiGe BiCMOS process.

To achieve conductive and wear-durable carbon thin films by metal doping, we deposited Au-, Pt-, and Pd-doped carbon thin films by RF sputtering, and evaluated the dopant concentrations, resistivity, and scratch hardness. Among the doped films, the Pt-doped film with low Pt concentration was most suitable from a practical perspective.

Output voltage regulation problem of DC-DC boost power converters is studied based on an averaged model with a practical inductor. This paper exploits the effect of inductor's parasitic resistance on the performance of an existing parallel-damped (PD) passivity-based controller (PBC) under load variations. As an attempt to apply the passivity-based framework to the converter with parasitic resistance we have combined a new proportional-integral (PI) controller with the PBC. Simulation results show that the combined (PBC and PI) dynamic output feedback controller successfully achieves the performance improvement under reference step changes and load variations.

This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32 nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32 nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.

We introduce the "split padding" into a current Merkle-Damgård hash function H. The patched hash function satisfies the following properties: (i) is second-preimage-resistant (SPR) if the underlying compression function h satisfies an "SPR-like" property, and (ii) is one-way (OW) if h satisfies an "OW-like" property. The assumptions we make about h are provided with simple definitions and clear relations to other security notions. In particular, they belong to the class whose existence is ensured by that of OW functions, revealing an evident separation from the strong collision-resistance (CR) requirement. Furthermore, we get the full benefit from the patch at almost no expense: The new scheme requires no change in the internals of a hash function, runs as efficiently as the original, and as usual inherits CR from h.

Electrical contacts are the most important parts of electrical circuits, and many reliability problems of the circuits are related to contact failure. The contact resistance is one of the important factors for assessing connector reliability, and thus the prediction of contact resistance is essential to designing electrical terminals. In this study, embossments, each 1 mm to 3 mm in radius, were brought into contact with flat planes to simulate the point of contact on a terminal, and the contact resistance was measured using a four-probe method under a load up to 40 N. Copper alloy samples, each plated with tin or silver and having an embossment of 1 mm to 3 mm in radius, were used and the visually clear indentations resulting from the embossment to plane contact were measured to determine their areas. Since the contact resistance is dependent on the contact area, an FEM analysis must be carried out to determine the contact areas correctly. In this paper, an elasto-plastic FEM analysis was performed taking the plating layers into account, and a method was established to make precise determination of the contact areas for different shapes of contacts and loads. The resultant contact areas were used to calculate the contact resistance, which showed a good agreement with experimental results. It was established that the load-resistance curves can be predicted on the basis of the shapes of the contacts as well as plating.

This study involves implementing an intelligent controller using the fuzzy control algorithm to minimize cold weld and splash in inverter AC spot welding. This study presents an experimental curve of a welding output current and the maximum value of the Instantaneous Heating Rate (IHRmax) using the contact diameter of an electrode as the parameter. It also presents the experimental curve of a welding output current and the slope (S) of the instantaneous dynamic resistance using the instantaneous contact area of an electrode as the parameter. To minimize cold weld and splash, this study proposes an intelligent controller that controls the optimum welding current in real time by estimating the contact diameter of an electrode and the contact area of the initial welding part.

The electromagnetic fields emitted from an electrostatic discharge (ESD) event occurring between charged metals cause seriously damage high-tech equipment. In order to clarify the generation mechanism of such ESD fields and also to reduce them, we previously proposed a finite-difference time-domain (FDTD) algorithm based on a delta-gap feeding method and a frequency dispersion characteristic formula (Naito's formula) of ferrite material for simulating the ESD fields due to a spark between the charged metals with ferrite core attachment. In the present study, by integrating the above FDTD algorithm and a spark-resistance formula, we simulated both of the ESD itself and the resultant fields for the metal bars with ferrite core attachment, and demonstrated that the core attachment close to the spark gap suppresses the magnetic field level. This finding was also validated via 6-GHz wide-band measurement of the magnetic near-field.

We have evaluated the tunneling contact resistivity based on numerical calculation of tunneling current density across an AlGaN barrier layer in non-polar AlGaN/GaN heterostructures. In order to reduce the tunneling contact resistivity, we have introduced an n+-AlXGa1 - XN layer between an n +-GaN cap layer and an i-AlGaN barrier layer. The tunneling contact resistivity has been optimized by varying Al composition and donor concentration in n+-AlXGa1-XN. Simulation results show that the tunneling contact resistivity can be improved by as large as 4 orders of magnitude, compared to the standard AlGaN/GaN heterostructure.

The paper demonstrates a novel two-peak negative differential resistance (NDR) circuit combining Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Compared to the resonant-tunneling diode, MOS-HBT-NDR has two major advantages in our circuit design. One is that the fabrication of this MOS-HBT-NDR-based application can be fully implemented by the standard BiCMOS process. Another is that the peak current can be effectively adjusted by the controlled voltage. The peak-to-valley current ratio is about 4136 and 9.4 at the first and second peak respectively. It is very useful for circuit designers to consider the NDR-based applications.

This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-µm CMOS process. The proposed ADC consumes 180 mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.59 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.

The sub-threshold R-MOSFET resistor structure which enables tuning range extension below the threshold voltage in the MOSFET with moderate to weak inversion operation is analyzed in detail. The principal operation of the sub-threshold resistor is briefly described. The analysis of its characteristic based on approximations of a general MOS equation valid for all regions is given along with discussion on design implication and consideration. Experiments and simulations are provided to validate the theoretical analysis and design, and to verify the feasibility at a supply voltage as low as 0.5 V using a low-threshold devices in a 1.8-V 0.18 µm CMOS process.

This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified with various length, shunt conductance and resistive termination. We also apply the proposed model to design space exploration, and demonstrate that the proposed model helps estimate the optimal shunt conductance and resistive termination according to required signaling length and throughput.

This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.

Characteristics of conductive elastomer that is composed of silicone rubber and dispersed carbon black particles show conductive and elastic properties in one simple material. This material has been widely applied to make-break contacts of panel switches and connectors of liquid crystal panels. However, since surface state of the contact is very soft, it is difficult to remove contaminant films of contaminated opposite side contact surface and to obtain low contact resistance owing to break the film. This is an important problem to be solved not only for the application of make-break switching contact but also static connector contacts. This study has been conducted to examine some complex structures of the elastomer which indicate removal characteristics for contaminant films and low contact resistance. As specimens, six different types of elastomer contacts composed of different type of dispersed materials as carbon and metal fibers, metal mesh, and plated surfaces were used. The contacts of opposite side were Au and Sn plated contact surface on a printed circuit board (PCB) which is usually used in the static connector and make-break contacts. In order to contaminate contact surfaces of PCB, the surfaces were subjected to exposure in an SO2 gas environment. The elastomeric contacts contained hard materials showed lower contact resistance than only dispersed carbon particles in the elastomer matrix for both contaminated PCB contact surfaces.

This paper reports on the effect of switching action on the contact surfaces of earthquake disaster prevention relays. Large-scale earthquakes occur frequently in Japan and bring extensive damage with them, and fire caused by electrical equipments is one example of the serious damage which can occur. Earthquake sensors capable of maintaining a high level of reliability when earthquakes occur play an important role as a means of minimizing this damage. For this reason, we carried out observations by focusing on samples which had either been subjected to an electric current of 10 mA or 0.1 A. The samples of 10 mA exhibited low and constant contact resistance despite the addition of seismic motion, while the samples of 0.1 A samples exhibited varying contact resistance and damage on their contact spots resulting from the addition of seismic motion. The sample surfaces were then observed using an atomic force microscope (AFM) in tapping mode and a surface potential microscope (SPoM). As a result, we found that even the unused earthquake disaster prevention relay (standard sample) which had a surface lined with asperities on its parallel striations formed by irregular protrusions due to dust and other deposits. In addition, scanning the contact surface with the SPoM at the same potential revealed the occurrence of differences in surface potential which varied in response to the asperities on the striations.