We proposed a hard-wired CPG hardware network to reproduce the gaits of four-legged animals. It should reproduce walking and bounding, and they should be switchable with each other by changing the value of only one voltage.

We considered the oxygen diffusivity around a conductive filament of resistive switching oxides, with the aim of designing material appropriate for highly reliable non-volatile memory. Both theoretical and experimental analyses were performed for this consideration. The theoretically obtained oxygen chemical potential difference, which works as a driving force for diffusion, significantly depends on a material. Then, we experimentally confirmed that the oxygen diffusion behaviors vary greatly depending on the chemical potential differences.

There has been increasing demand to research the measuring method to characterize the batch consistency of contact rivets. An automated test equipment has been described that makes it possible to measure the electrical contact resistance with high efficiency. The relationship between contact force and contact resistance during the loading and unloading process was measured explicitly using AgPd alloy, stainless steel and sapphire substrate material with Au coatings as sphere indenters separately. To explain the phenomena of contact resistance decreasing more slowly than the traditional theoretical results during loading, the indenter with coating and rivet are modeled by using the commercial FEM software COMSOL Multiphysics. Besides the constriction resistance, the transition region Au coating resistance and the bulk resistance of the substrate are deduced from the simulated current lines profiles and iso-potentials. The difference of electrical conductivity between indenter material and gold coating is the reason for the occurrence of the transition region.

In the design of distributed systems, defending against Sybil attack is an important issue. Recently, OSN (Online Social Network)-based Sybil defending approaches, which use the fast mixing property of a social network graph with sufficient length of random walks and provide Sybil-resistant trust values, have been proposed. However, because of the probabilistic property of the previous approaches, some honest (non-Sybil) identities obtain low trust value and they are mistakenly considered as Sybil identities. A simple solution of boosting the trust value of honest identities is using longer random walks, but this direct boosting method also increases trust values of Sybil identities significantly. In this paper, a two-step boosting method is proposed to increase the Sybil-resistant trust value of honest identities reasonably and to prevent Sybil identities from having high trust values. The proposed boosting method is composed of two steps: initializing the trust value with a reasonably long random walks and boosting the trust value by using much longer random walks than the first step. The proposed method is evaluated by using sampled social network graphs of Facebook, and it is observed that the proposed method reduces the portion of honest identities mistakenly considered as Sybil identities substantially (from 30% to 1.3%) and keeps the low trust values of Sybil identities.

This paper presents a novel decoupling network consisting of transmission lines and a bridge resistance for a two-element array antenna and evaluates its performance through simulations and measurements. To decouple the antennas, the phase of the mutual admittance between the antenna ports is rotated by using the transmission lines, and a pure resistance working as a bridge resistance is inserted between the two antenna ports to cancel the mutual coupling. The simulation results indicate that the proposed decoupling network can provide a wider bandwidth than the conventional approach. The proposed decoupling network is implemented and tested as a demonstration to confirm its performance. The measurement results indicate that the mutual coupling between the two antenna ports is lowered by about 47dB at the resonant frequency.

A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.

A low VDD current mirror with deep sub-micron vertical MOSFETs is presented. The keys are new bias circuits to reduce both the minimum VDD for the operation and the sensitivity of the output current on VDD. In the simulation, our circuits reduce the minimum VDD by about 17% and the VDD sensitivity by one order both from those of the conventional. In the simulation with 90nm φ vertical MOSFET approximate models, our circuit shows about 4MΩ output resistance at 1.2-V VDD with the small temperature dependence, which is about six times as large as that with planar MOSFETs.

The delay time component (τs) of an InGaAs MOSFET caused by dynamic source resistance is discussed. On the basis of the relationship between the current density (J) and the dynamic source resistance (rs), the value of rs is proportional to 1/J with some offset at low current densities, whereas the offset becomes smaller in a region of high current density. The value of τs depends on the current in a way similar to rs. Because the offset in the high-current-density region is proportional to the square root of the effective mass, an InGaAs MOSFET with a small mass has a shorter rs than a Si MOSFET.

A high-speed and low-power 8-bit subranging analog-to-digital converter (ADC) based on 65-nm CMOS technology was fabricated. Rather than using digital foreground calibration, an analog-centric approach was adopted to reduce power dissipation. An offset cancelling charge-steering amplifier and capacitive-averaging technique effectively reduce the offset, noise, and power dissipation of the ADC. Moreover, the circuit used to compensate the kickback noise current from the comparator can also reduce the power dissipation. The reference-voltage generator for the fine ADC is composed of a fine ladder and a capacitor providing an AC signal path. This configuration reduces the power dissipation of the selection signal drivers for the analog multiplexer. A test chip fabricated using 65-nm digital CMOS technology achieved a high sampling rate of 1GHz, a low power dissipation of 17.5mW, and a figure of merit of 118fJ/conv.-step.

Multi-Walled CNT (MWCNT) are synthesized on a silicon wafer and sputter coated with a gold film. The planar surfaces are mounted on the tip of a piezo-electric actuator and mated with a gold coated hemispherical surface to form an electrical contact. These switching contacts are tested under conditions typical of MEMS relay applications; 4V, with a static contact force of 1mN, at a low current between 20-50mA. The failure of the switch is identified by the evolution of contact resistance which is monitored throughout the switching cycles. The results show that the contact resistance can be stable for up to 120 million switching cycles, which are 106 orders of higher than state-of-the-art pure gold contact. Bouncing behavior was also observed in each switching cycle. The failing mechanism was also studied in relation to the contact surface changes. It was observed that the contact surfaces undergo a transfer process over the switching life time, ultimately leading to switching failure the number of bounces is also related to the fine transfer failure mechanism.

We have investigated the impact of O2 annealing after SiOx deposition on the switching behavior to gain a better understanding of the resistance switching mechanism, especially the role of oxygen deficiency in the SiOx network. Although resistive random access memories (ReRAMs) with SiOx after 300 annealing sandwiched with Pt electrodes showed uni-polar type resistance switching characteristics, the switching behaviors were barely detectable for the samples after annealing at temperatures over 500. Taking into account of the average oxygen content in the SiOx films evaluated by XPS measurements, oxygen vacancies in SiOx play an important role in resistance switching. Also, the results of conductive AFM measurements suggest that the formation and disruption of a conducting filament path are mainly responsible for the resistance switching behavior of SiOx.

We have fabricated Pt/Si-rich oxide (SiOx)/TiN stacked MIM diodes and studied an impact of the structural asymmetry on their resistive switching characteristics. XPS analyses show that a TiON interfacial layer was formed during the SiOx deposition on TiN by RF-sputtering in an Ar + O2 gas mixture. After the fabrication of Pt top electrodes on the SiOx layer, and followed by an electro-forming process, distinct bi-polar type resistive switching was confirmed. For the resistive switching from high to low resistance states so called SET process, there is no need to set the current compliance. Considering higher dielectric constant of TiON than SiOx, the interfacial TiON layer can contribute to regulate the current flow through the diode. The clockwise resistive switching, in which the reduction and oxidation (Red-Ox) reactions can occur near the TiN bottom electrode, shows lower RESET voltages and better switching endurance than the counter-clockwise switching where the Red-Ox reaction can take place near the top Pt electrode. The result implies a good repeatable nature of Red-Ox reactions at the interface between SiOx and TiON/TiN in consideration of relatively high diffusibility of oxygen atoms through Pt.

Experiments were carried out at several voltages to clarify the influence of the voltage on various characteristics, i.e. arc duration, contact resistance, arc energy, and the change in electrode mass. The voltage was varied from DC100 V to 160 V, the load current was fixed at 5 A constant, and the electromagnetic contactor was operated continuously up to 100,000 times. The experiments were carried out under the three operation modes which are classified by the arc discharge. As a result, the relation between the operation mode and contact resistance was clarified. When only a make arc was generated, the contact resistance was smallest. In addition, the contact resistance was not affected by the source voltage.

Tin (Sn) contacts are widely applied to connector contacts. Surfaces of plated tin layer are covered with an oxide film that results in high contact resistance. However, it is possible to obtain low contact resistance by using high contact load. Current downsizing trends often make it difficult to obtain high contact loads. Therefore, it is important to conduct basic studies of the contacts resistance characteristics under low contact load conditions. In this study, relationships between contact resistance and the changes of contact traces were examined. When a platinum (Pt) hemisphere contacted to tin plated flat coupon, it was found that the hemisphere surface sank into the softer tin plated flat surface during loading resulting in a piling up tin crystal grains along the periphery of the contact trace. During this process, sudden decrease in contact resistance was observed. To clarify the phenomenon, morphology changes of contact traces were observed by AFM, SEM and EBSD. FEM analysis was also used to analyze the mechanical stress distribution in the tin plated layer. Due to the peculiar distribution of stress, the crystal grains are separated and push out the contact area. This phenomenon is very different from commonly observed decrease in contact resistance due to elastic and plastic deformation inducing mechanical fracture of the surface oxide film.

Current collapse of AlGaN/GaN heterostructure field-effect transistors (HFETs) formed on qualified epitaxial layers on Si substrates was successfully suppressed using graded field-plate (FP) structures. To improve the reproducibility of the FP structure manufacturing process, a simple process for linearly graded SiO2 profile formation was developed. An HFET with a graded FP structure exhibited a significant decrease in an on-resistance increase ratio of 1.16 even after application of a drain bias of 600 V.

This paper proposes a write resistance tracking circuit (WRTC) to improve the memory window of HfOx-based resistive memory. With a 50-ns single voltage pulse, the minimal resistance of the high resistance state in the 1-kb array of resistive switching elements can increase from 25 kΩ to 65 kΩ by using the proposed verify circuit. The WRTC uses the transition current detection method based on the feedback of the memory cell to control the write driver. The WRTC achieves distinct bistable resistance states, avoids the occurrence of over-RESET, and enhances the memory window of the RRAM cell.

In this work, the effect of device dimension variation and metal wiring scheme on the RF performance of MOSFETs based on 0.13-µm RFCMOS technology has been investigated. Two sets of experiments have been carried out. In the first experiment, two types of source metal wiring options, each with various gate poly pitches, have been investigated. The results showed that the extrinsic capacitances (Cegs, Cegd) and parasitic resistances tend to increase with increasing gate poly pitch. Both cutoff frequency (fT) and maximum oscillation frequency (fmax) showed substantial degradation for the larger gate poly pitches. Based on measurement, we propose a simplified model for extrinsic parasitic capacitance as a function of gate poly pitch with different source metal wiring schemes. For the second experiment, the impact of gate metal wiring scheme and the number of gate fingers Nf on the RF performance of MOSFET has been studied. Two different types of gate metal wiring schemes, one with poly layer and the other with M2 layer, are compared. The measurement showed that the capacitance is slightly increased, while gate resistance significantly reduced, with the M2 gate wiring. As a result, fT is slightly degraded but fmax is significantly improved, especially for larger Nf, with the M2 gate wiring. The results in this work provide useful information regarding device dimension and metal wiring scheme for various RF applications of RF CMOS technology.

In the current study, stress-induced capacitance determined by direct measurement on MOSFETs was compared with that determined by indirect simulation through the delay of CMOS ring oscillators (ROs) fabricated side by side with MOSFETs. External compressive stresses were applied on <110> silicon-on-insulator (SOI) n-/p-MOSFETs with the ROs in a longitudinal configuration. The measured gate capacitance decreased as the compressive stress on SOI increased, which agrees with the result of the capacitance difference between measured and simulated delay of the ROs. The oscillation frequency shift of the ROs should mainly be attributed to oxide capacitance, aside from the change in mobility of the n-/p-MOSFETs. The result suggests that the stress-induced gate capacitance of partially depleted MOSFETs is an important factor for the capacitance shift in a circuit and that ROs can be used in a vehicle to determine mechanical stress-induced gate capacitance in MOSFETs.

We have studied resistance-switching properties of RF sputtered Si-rich oxides sandwiching with Pt electrodes. By sweeping bias to the top Pt electrode, non-polar type resistance switching was observed after a forming process. In comparison to RF sputtered TiOx case, significant small current levels were obtained in both the high resistance state (HRS) and the low resistance state (LRS). And, even with decreasing SiOx thickness down to 8 nm from 40 nm, the ON/OFF ratio in resistance-switching between HRS and LRS as large as 103 was maintained. From the analysis of current-voltage characteristics for Pt/SiOx on p-type Si(100) and n-type Si(100), it is suggested that the red-ox (REDction and OXidation) reaction induced by electron fluence near the Pt/SiOx interface is of importance for obtaining the resistance-switching behavior.

Superconducting integrated circuits should be operated at low temperature below a half of their critical temperatures. Thermal heat from a bias resistor could rise the temperature in Josephson junctions, and would reduce their critical currents. In this study, we estimate the temperature in a Josephson junction heated by a bias resistor at the bath temperature of 4.2 K, and introduce a parameter β that connects the thermal heat from a bias resistor and the temperature elevation of a Josephson junction. By using β, the temperature in the Josephson junction can be estimated as functions of the current through the resistor.