We studied planar graded-gap injector GaAs Gunn diodes designed for operation at 94 GHz. Two types of planar Gunn diodes were designed and fabricated. In the first diode, a cathode was situated inside a circular anode with a diameter of 190 µm. The distance between the anode and cathode varied from 60 µm to 68 µm depending on the cathode size. Also, we designed a structure with a constant distance between the anode and cathode of 10 µm. In the second diode, the anode was situated inside the cathode for the flip-chip mounting on the oscillator circuits. The fabrication of the Gunn diode was based on ohmic contact metallization, mesa etching, and air-bridge and overlay metallization. DC measurements were carried out, and the nature of the negative differential resistance, the operating voltage, and the peak current in the graded-gap injector GaAs Gunn diodes are discussed for different device structures. It is shown that the structure with the shorter distance between the cathode and anode has a higher peak current, higher breakdown voltage, and lower threshold voltage than those of the structure with the larger distance between the cathode and anode.

Unforgeability of digital signatures is closely related to the security of hash functions since hashing messages, such as hash-and-sign paradigm, is necessary in order to sign (arbitrarily) long messages. Recent successful collision finding attacks against practical hash functions would indicate that constructing practical collision resistant hash functions is difficult to achieve. Thus, it is worth considering to relax the requirement of collision resistance for hash functions that is used to hash messages in signature schemes. Currently, the most efficient strongly unforgeable signature scheme in the standard model which is based on the CDH assumption (in bilinear groups) is the Boneh-Shen-Waters (BSW) signature proposed in 2006. In their scheme, however, a collision resistant hash function is necessary to prove its security. In this paper, we construct a signature scheme which has the same properties as the BSW scheme but does not rely on collision resistant hash functions. Instead, we use a target collision resistant hash function, which is a strictly weaker primitive than a collision resistant hash function. Our scheme is, in terms of the signature size and the computational cost, as efficient as the BSW scheme.

Further development of a network based on the Inverse Function Delayed (ID) model which can recall temporal sequences of patterns, is proposed. Additional advantage is taken of the negative resistance region of the ID model and its hysteretic properties by widening the negative resistance region and letting the output of the ID neuron be almost instant. Calling this neuron limit ID neuron, a model with limit ID neurons connected pairwise with conventional neurons enlarges the storage capacity and increases it even further by using a weightmatrix that is calculated to guarantee the storage after transforming the sequence of patterns into a linear separation problem. The network's tolerance, or the model's ability to recall a sequence, starting in a pattern with initial distortion is also investigated and by choosing a suitable value for the output delay of the conventional neuron, the distortion is gradually reduced and finally vanishes.

This paper addresses the on-resistance (Ron) extraction of the DMOS based driver in Power IC designs. The proposed method can extract Ron of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to Ron. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.

In this article, we discuss the security of double-block-length (DBL) hash functions against the free-start collision attack. We focus on the DBL hash functions composed of compression functions of the form F(x) = (f(x), f(p(x))), where f is a smaller compression function and p is a permutation. We first show, in the random oracle model, that a significantly good upper bound can be obtained on the success probability of the free-start collision attack with sufficient conditions on p and the set of initial values. We also show that a similar upper bound can be obtained in the ideal cipher model if f is composed of a block cipher.

In this paper, we study multi-collision probability. For a hash function H :D R with |R|=n, it has been believed that we can find an s-collision by hashing Q=n(s-1)/s times. We first show that this probability is at most 1/s! for any s, which is very small for large s (for example, s=n(s-1)/s). Thus the above folklore is wrong for large s. We next show that if s is small, so that we can assume Q-s ≈ Q, then this probability is at least 1/s!-1/2(s!)2, which is very high for small s (for example, s is a constant). Thus the above folklore is true for small s. Moreover, we show that by hashing (s!)1/sQ+s-1 (≤ n) times, an s-collision is found with probability approximately 0.5 for any n and s such that (s!/n)1/s ≈ 0. Note that if s=2, it coincides with the usual birthday paradox. Hence it is a generalization of the birthday paradox to multi-collisions.

Many researchers have attempted to solve the combinatorial optimization problems, that are NP-hard or NP-complete problems, by using neural networks. Though the method used in a neural network has some advantages, the local minimum problem is not solved yet. It has been shown that the Inverse Function Delayed (ID) model, which is a neuron model with a negative resistance on its dynamics and can destabilize an intended region, can be used as the powerful tool to avoid the local minima. In our previous paper, we have shown that the ID network can separate local minimum states from global minimum states in case that the energy function of the embed problem is zero. It can achieve 100% success rate in the N-Queen problem with the certain parameter region. However, for a wider parameter region, the ID network cannot reach a global minimum state while all of local minimum states are unstable. In this paper, we show that the ID network falls into a particular permanent oscillating state in this situation. Several neurons in the network keep spiking in the particular permanent oscillating state, and hence the state transition never proceed for global minima. However, we can also clarify that the oscillating state is controlled by the parameter α which affects the negative resistance region and the hysteresis property of the ID model. In consequence, there is a parameter region where combinatorial optimization problems are solved at the 100% success rate.

In this letter, the fabrication of a compact and high performance semi-lumped coplanar waveguide low-pass filter (CPW-LPF) on high resistivity silicon (HRS) substrate at millimeter wave is proposed. The design procedure and the equivalent circuit of the proposed semi-lumped CPW-LPF is discussed. The filter structure of is very simple but its performances is fairly good. This designed filter at cutoff frequency fc of 31 GHz has very good measured characteristics including the low insertion loss, sharp rejection and low group delay, due to the reduced substrate loss of HRS. Experimental results of the fabricated filter show a good agreement with the predicted results.

Distortion characteristics caused by the thermal memory effect in power amplifiers were accurately predicted using a multi-stage thermal RC-ladder network derived by simplifying the heat diffusion equation. Assuming a steep gradient of heat diffusion near an intrinsic transistor region in a semiconductor substrate, the steady state temperature, as well as the transient thermal response at the transistor region, was estimated. The thermal resistances and thermal capacitances were adjusted to fit a temperature distribution characteristic and a step response characteristic of temperature in the substrate. These thermal characteristics were calculated by thermal FDTD simulation. For an InGaP/GaAs HBT, a step response characteristic for a square-wave voltage signal input was simulated using a large-signal model of the HBT connecting the multi-stage thermal RC-ladder network. The result was verified experimentally. Additionally, for an RF-amplifier using the HBT, the 3rd-order intermodulation distortion caused by the thermal memory effect was simulated and this result was also verified experimentally. From these verifications, a multi-stage thermal RC-ladder network can be used to accurately design super linear microwave power amplifiers and linearizers.

Contact resistance is caused by constriction resistance and film resistance through contact layers. It is well known that a surface film causes non-linear voltage and current characteristics. The origin of non-linearity is caused by tunneling electron through thin insulation barrier or jumping over the thick barrier (Shottky barrier) on the contact surface. In this paper, a new idea causing nonlinear property by only current constriction which flows through very small contact spot area, if there is no film layer, is proposed by the two dimensional contact model. The contact model, used in this paper, is a two dimensional type narrow path of contact area (short bridge) made by thin copper foil of 0.035 mm on a glass epoxy resin board. The contact part is made by scraping with an electric drill as a single bridge shape of 0.1 mm wide and 0.3 mm long on the centre of a board (100 mm100 mm). The 3rd harmonic distortion voltage was measured by using a Component Linearity Test Equipment (Type CLT1 made by Radiometer Electronics Company) which the system supplies a pure sine wave current of 10 kHz and detects a distortion voltage of 30 kHz by a narrow band pass filter circuit. The sensitivity of the Component Linearity Test Equipment (CLT1) is under a 10-9 volt. Four bridge samples were examined for the comparison of nonlinear distortion voltage. The distortion voltage of a sample (A) (0.1 mm wide, 0.3 mm long) is too larger than the one of the sample (B) (0.2 mm wide, 0.3 mm long) at the same applied voltage which resistance is not so different each other. It seems that current constriction to the spot (A) may heat up higher and cool down lower than (B). It would be also guessed that the power dissipation of 20 kHz cause temperature oscillation of 20 kHz, then it causes a component of contact resistance of 20 kHz, and therefore the product of 10 kHz current and 20 kHz resistance component cause 30 kHz component distortion voltage.

There are two interesting phenomena for the electrical contact characteristics of YBCO bulk. One is the transition between low and high contact resistance states at a threshold current value which is called a transfer current; the other is the forming reason of the residual resistance when the carrying current is lower than the transfer current. In this paper, an axial symmetric model is constructed to investigate these two phenomena. During the calculation, the thermal field, the electrical field and the self magnetic field are coupled with each other. The detailed fields' distributions are obtained. The calculation results are accordance with the experimental results. And some useful conclusions are drawn based on the numerical analyses.

A persistent current switch (PCS) is used for superconducting applications, such as superconducting magnetic energy storage (SMES) system. The authors have proposed a mechanical switch of Y-Ba-Cu-O (YBCO) bulk as a mechanical PCS. In previous study, the authors have successfully reduced a residual resistance by depositing with metal on contact surface. This paper focused on a current carrying area (called a-spot) on contact surface and presented an effect of deposited metal on electrical contact characteristics in order to clear the contact mechanism. As the results of experiments and simulation using FEM, it became clear that it was effective for reducing the residual resistance from a view point of increasing the a-spot by depositing with metal.

The possibility of using three kinds of new type composite materials as material for high speed sliding contacts was investigated. The results of this investigation were compared with the results of the low speed tests that were reported earlier. As a result of the above, it was discovered that for high speed rotation in the range from 0.014 m/s to 2 m/s, the order of merit did not significantly change. Based on this, it was concluded that if solid lubricant is effectively supplied to the sliding surface, the influence by frictional heat generated by high speed is slight. Of the three kinds of composite material, it was clarified that composite material (CMML-1) had the lowest contact resistance and Composite Material (CMML-3) had the lowest maximum frictional coefficient of friction. 'CM' and 'ML' are initialisms for 'Composite Material' and 'Material of Lubrication' respectively. The number that is attached to the material name is a numeric value that was set by this laboratory.

In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor (SC) circuits, especially multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters. Theory and simulation results reveal that the settling time of MDACs can be decreased by optimizing the switch resistances. This switch resistance optimization does not only effectively increase the speed of single-bit MDACs, but also of multi-bit MDACs. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. With such an optimization, the response of the switch will be improved by up to 50%.

As the basic study of the electromagnetic interference (EMI) problem at the circuit elements, the near magnetic field distributions above resistors for the termination of a transmission line are measured to reveal the profile of radiation. Five kinds of resistors and two types of resistance values are sampled. The results showed that the variation of the near magnetic field distribution above the transmission line is effected largely by the reactance of the resistor at the high frequency. These results are the basis for the design of the structure of the component.

The dry etching resistance of ArF resist patterns was improved by irradiating vacuum ultraviolet (VUV) light with a wavelength of 172 nm to ArF resist patterns in N2 atmosphere. The density of C=O bonds of the resists is decreased, and the dry etching rate of resist is also decreased after VUV irradiation. The line width shrinkage by the electron beam irradiation of CD-SEM was greatly improved from 9 nm to 2 nm, and LER (Line Edge Roughness) of resist patterns was approximately 2 nm improved from 8.4 nm to 6.5 nm under VUV irradiation. Using VUV cure, the dry etching pattern of a SiN film showed a rectangle-like cross-sectional view, and indicated almost the same LER value as the resist mask pattern. The VUV cure technique is an attractive method of fine resist pattern fabrication by ArF lithography.

This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.

A color filter is the penetrable device adhering red, green, and blue organic color resists onto the surface of glass substrate for application of liquid crystal displays. It is fabricated by several technologies, including lithographic processes of coating, baking, exposing, etching, and rinsing. Inkjet printing technology has potentially implemented on the fabrication of the large-size panel with organic molecular film since this technology offers an efficient and steady production procedure. To achieve the basic specifications and requirements of high color performance, high color purity, high flatten, low reflective, and low production cost, inkjet printing technology will be seriously considered in the color filter manufacturing. Here we present the experimental results on physical and chromatic characteristics of color filters by implementing inkjet printing technology. To verify the chromatic characteristics of the resultant color filters, CIE 1931 chromaticity diagram is adopted to present the coordination of color distribution. For the green color ink, the results are x=0.30950.04, y=0.59120.04, brightness of Y=58.887 for 50 droplets and x=0.31030.04, y=0.57840.04, brightness of Y=60.328 for 41 droplets. For the blue color ink, the result is x=0.14900.04, y=0.10150.04, brightness of Y=8.808. For the red color ink, the result is x=0.5720.04, y=0.3200.04, brightness of Y=27.1.

This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.

A network based on the Inverse Function Delayed (ID) model which can recall a temporal sequence of patterns, is proposed. The classical problem that the network is forced to make long distance jumps due to strong attractors that have to be isolated from each other, is solved by the introduction of the ID neuron. The ID neuron has negative resistance in its dynamics which makes a gradual change from one attractor to another possible. It is then shown that a network structure consisting of paired conventional and ID neurons, perfectly can recall a sequence.