High-frequency characterization and delay-time analysis have been performed for a short channel AlGaN/GaN heterojunction FET. The fabricated device with a short gate length (Lg) of 0.07 µm exhibited an extrinsic current gain cutoff frequency of 81 GHz and a maximum frequency of oscillation of 190 GHz with a maximum stable gain (MSG) of 8.2 dB at 60 GHz. A new scheme for the delay-time analysis was proposed, in which the effects of rather large series resistance RS + RD are properly taken into account. By applying the new scheme to a device with Lg=0.25 µm, we obtained an effective high-field electron velocity of 1.75107 cm/s, which is consistent with our previous results calculated using Monte Carlo simulation.

InGaP/GaAs HBT with novel ledge coupled capacitor (LCC) structure has been proposed and demonstrated for the first time. The LCC employs an extrinsic InGaP ledge layer as a capacitor parallel to the base resistor. This configuration enables feeding RF signals directly into the base without passing them through the base resistor. With the fabricated HBT, no increase of leakage current between emitter and base electrode was observed. The maximum oscillation frequency (fmax) of the HBT was improved by 10 GHz as compared with an HBT without the LCC.

The concept of an Ω-matrix was introduced by Nishi in order to estimate the number of solutions of a resistive circuit containing active elements. He gave a finite characterization by means of four conditions which are all satisfied if and only if the matrix under investigation is an Ω-matrix. In this note we show that none of the four conditions can be omitted.

A constant voltage/constant current (CV/CC) parallel operation heterojunction bipolar transistor (HBT) power amplifier (PA) configuration is presented, and its design method is described. A resistor base feed (CC mode) HBT is connected to an inductor base feed (CV mode) HBT in parallel, and compensates the gain expansion of the CV mode HBT due to near class-B operation. By adding CC mode HBT, the total quiescent current can be decreased from 32 mA to 23 mA with adjacent channel leakage power ratio (ACPR) < -40.0 dBc. At the maximum output power region, the fabricated PA achieves output power (Pout) of 26.8 dBm and power added efficiency (PAE) of 42.0% with ACPR of -40.0 dBc, and shows the comparable performances with a conventional PA using CV mode HBT.

The frequency dependence of surface resistance Rs of high temperature superconductor (HTS) films are measured by a novel measurement method using four TE0mp modes in a sapphire rod resonator. At first, a loss tangent tan δ of the sapphire rod and Rs of the HTS films are evaluated separately from the results measured for the TE021 and TE012 modes with close resonant frequencies. Secondly, Rs values at two different resonant frequencies for the TE011 and TE022 modes are measured using a well-known relation for sapphire tan δ/f = constant, where f is a frequency. Rs values of HoBa2Cu3O7-x thin films were measured in the frequency range of 10 to 43 GHz by using four sapphire rod resonators with different sizes. As a result, it is found that these measured results of Rs have a characteristic of frequency square.

In recent years, sliding electric contacts came to be often used under very severe conditions such as high temperature, extremely low temperature, high vacuum, etc. Conventionally, solid lubricants having excellent properties in lubricating performance are generally used compositely with a metal of high electric conductivity, because of their high electrical resistivity. In the present study, we proved that more excellent sliding electrical contacts can be produced with a design made by controlling the distribution on contact surface of a solid lubricant having excellent lubricating performance and of a metal with high electric conductivity through expansion of Greenwood's theory.

In this paper, we try to establish a power law for contact resistance versus force Rc = KcFc-n , and we determine via experimental measurements and theoretical calculations, the constants n and Kc in the force range (1 mN-4 N) for bulk metal (Ag, Au, Pd, Ni) used in various applications (microswitches, connectors). The main experimental results of contact resistance are the occurrence of two decrease domains versus progressive load indentation. The first regime corresponds to the earlier touch of the coupon by the probe at force < 0.1 N. This elastic regime evolves to a plastic regime for medium force > 0.1 N. At the transition the exponent value n changes from 0.33 to 0.5 and induce Kc value increasing. Theoretical and computational approaches applied to the elasto-plastic model, confirm the occurrence of these two regimes. Although the calculated values of n are in good agreement with experimental values, some discrepancy between measured and calculated Kc values take place.

An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.

The potential drop and the self-heating due to the contact resistance at the interface between silicide and silicon are incorporated in the device simulation for ESD protection devices. A transition region is provided at the interface and the resistivity is calculated by scaling the contact resistance by the length of the region. The power density used in the heat conductive equation is calculated by using the potential drop and the contact resistance in the transition region. The validity of the present approach is checked by the Monte Carlo simulations. Using the technique, influence of the contact resistance on self-heating in an ESD protection device with the grounded gate MOSFET structure is simulated.

In this paper, we propose the CMOS implementation of neuron models for an artificial auditory neural network. We show that when voltage is added directly to the control terminal of the basic circuit of the hardware neuron model, a change in the output firing is observed. Next, based on this circuit, a circuit that changes with time is added to the control terminal of the basic circuit of the hardware neuron model. As a result, a neuron model is constructed with ON firing, adaptation firing, and repetitive firing using CMOS. Furthermore, an improved circuit of a neuron model with OFF firing using CMOS which has been improved from the previous model is also constructed.

This paper describes a three-port power divider with compensation networks for non-ideal isolation resistor. The compensation networks consist of two pairs of transmission lines and cancel out the parasitic reactance of the non-ideal isolation resistor. The design equations to provide perfect return loss and isolation at a center frequency are presented. The availability of the proposed power divider has been verified by the comparison between calculated and experimental results in the Ku-band.

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOSFET (FG-MOSFET) is proposed. First, the grounded VCLVR realization is discussed. The proposed circuit consists of only an ordinary MOSFET and an FG-MOSFET. The advantages of the proposed VCLVR are low-power and wide-input range and also the power consumption of the proposed VCLVR is the same as an ordinary passive resistor. The performance of the proposed circuits are confirmed by HSPICE simulations with a standard 0.6 µm CMOS process parameters. Simulations of the proposed VCLVR demonstrate a resistance value of 40 kΩ to 338 kΩ and an input range of 4.34 V within THD of less than 1.1%. Next, we proposed a new floating node linear variable resistor using the proposed VCLVR. The performance of the circuit is also evaluated through HSPICE.

In this paper, we propose a floating resistor circuit with positive and negative resistance operating at the low supply voltages 1.5 V. Only two transistors are connected between supply lines in order to operate under the low power supply voltages. In this circuit, current subtraction is carried out at the gate terminal for which input/output voltage is applied. As a result, the proposed circuit can realize the large range of resistance of positive and negative resistances. Therefore, in an application, the proposed circuit is used in neuro-based limit cycle generator as synaptic weights.

A new measurement method using two resonance modes, the TE021 and TE012 modes, in an image-type dielectric resonator is proposed to measure the surface resistance Rs of only one high-Tc superconductor (HTS) film and the loss tangent tan δ of a sapphire rod separately, precisely and nondestructively. The image-type resonator is constructed by placing a sapphire rod in a bottom of a conductor cavity made of two HTS films and a copper ring. This resonator is designed from the mode charts calculated on the basis of the rigorous analysis by the mode matching method, taking account of an uniaxial-anisotropic characteristic of sapphire. It is verified that the mode charts are also effective to identify many resonance modes observed in measurement. The temperature dependence of Rs of one YBCO film was measured at 19.3 GHz by this method. The measured result agreed very well with one measured by the conventional two-dielectric resonator method. As a result, it was verified that this method is useful to evaluate Rs value of one HTS film with no damage.

Software obfuscation is a promising approach to protect intellectual property rights and secret information of software in untrusted environments. Unfortunately previous software obfuscation techniques share a major drawback that they do not have a theoretical basis and thus it is unclear how effective they are. Therefore we propose new software obfuscation techniques in this paper. The techniques are based on the difficulty of interprocedural analysis of software programs. The essence of our obfuscation techniques is a new complexity problem to precisely determine the address a function pointer points to in the presence of arrays of function pointers. We show that the problem is NP-hard and the fact provides a theoretical basis for our obfuscation techniques. Furthermore, we have already implemented a prototype tool that obfuscates C programs according to our proposed techniques and in this paper we describe the implementation and discuss the experiments results.

Load/unload techniques are widely used in mobile hard disk drives which have to endure external shocks frequently. ABS designs must consider both the load/unload performance and the shock resistance performance. Three ABS designs with different positions of the suction force center are studied in simulation. It is observed that when the position of the suction force center moves frontward, the anti-shock performance improves, but the unload performance degrades, and vice versa. A slider is not necessary to be designed to have its suction force center significantly behind of its geometric center, as the traditional load/unload sliders do. Instead, the suction force center can be designed near the geometric center if the hook limiter is used.

The transient phenomenon of electromagnetic waves caused by a time dependent resistive screen in a waveguide is treated by using Wiener-Hopf technique. A boundary-value problem is formulated to describe the phenomenon, in which the resistivity of screen varies from infinite to zero in dependence on time. Application of the Fourier transformation with respect to time derives a Wiener-Hopf equation, which is solved by a commonly known decomposition procedure. The transient field is derived from the solution of the equation in terms of the Fourier inverse transform. By using the incomplete Lipschitz-Hankel integral for the computation of the field, numerical examples are given and the transient phenomenon is discussed.

A practical method of measuring the contact resistance of a phosphorus-doped poly-Si plug formed on a lightly phosphorus-doped diffusion region in DRAM memory cells is described. Contact resistance was obtained electrically, using ordinary contact-chain test structures, by changing the measurement of the substrate bias. This separated the bias-dependent resistance of the lightly doped diffusion layer from the total resistance. The method was used experimentally to evaluate the feasibility of forming low-resistance contacts down to a diameter of 130 nm for giga-bit DRAMs. Electrical measurement showed that reducing the interface resistance between the poly-Si plug and the lightly doped diffusion layer was effective for forming low-resistance contacts, though a specific interface layer could not be detected by TEM observation.

Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO2 interface and the resulting dopant loss during annealing is a common obstacle for antimony and arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimony pileup was suppressed with the RTA at relatively low temperature, such as 800 or 900. As a result, low sheet resistance of 260 Ω/sq. was obtained for a 24 nm depth junction with antimony. These results indicate that antimony is superior to arsenic as a dopant for ultra shallow extension formation. However, increase in antimony concentration above 11020 cm-3 gives rise to precipitation and it limits the sheet resistance reduction of the antimony doped junctions. Redistribution behaviors of antimony relating to the pileup and the precipitation are discussed utilizing SIMS (Secondary Ion Mass Spectrometry) depth profiles.

We report our studies on electrical current pulse perturbation of superconducting YBa2Cu3O7-x (YBCO) epitaxial thin films. When a current pulse is applied to a YBCO microbridge, a voltage develops across it that depends on the amplitude of the input current pulse. For a total current (input current pulse plus the dc bias) that is lower than the critical current Ic, an inductive voltage response is observed. When the total current exceeds Ic, a resistive response is generated and is observed after a certain delay time td. The origin of the resistive response was analyzed using the Geier and Schon model, which is based on the time-dependent Ginzburg-Landau equation. Our experimental samples consisted of 200-nm-thick epitaxial YBCO films, patterned into coplanar-strip (CPS) transmission lines, containing either two-microbridge or single-microbridge test structures. For the two-microbridge samples, a train of 100-fs-duration optical pulses was used to excite the larger microbridge and generate 2-ps-duration electrical pulses, which were then applied to perturb the smaller microbridge, which was independently biased in the superconducting state. In this case, an electro-optic sampling system was used to measure the YBCO kinetic-inductive voltage responses with the picosecond time resolution. For the single-microbridge structures, an electronic pulse generator was employed to supply the input current pulse, and a 14-GHz sampling oscilloscope was used to monitor the microbridge responses. The latter signals were in very good agreement with the model of Geier and Schon, assuming that the quasiparticle dynamics process that resulted from the nanosecond-wide current excitation was bolometric and followed the phonon escape time τes.