In this paper, we put forward the notion of a token-based multi-input functional encryption (token-based MIFE) scheme - a notion intended to give encryptors a mechanism to control the decryption of encrypted messages, by extending the encryption and decryption algorithms to additionally use tokens. The basic idea is that a decryptor must hold an appropriate decryption token in addition to his secrete key, to be able to decrypt. This type of scheme can address security concerns potentially arising in applications of functional encryption aimed at addressing the problem of privacy preserving data analysis. We firstly formalize token-based MIFE, and then provide two basic schemes; both are based on an ordinary MIFE scheme, but the first additionally makes use of a public key encryption scheme, whereas the second makes use of a pseudorandom function (PRF). Lastly, we extend the latter construction to allow decryption tokens to be restricted to specified set of encryptions, even if all encryptions have been done using the same encryption token. This is achieved by using a constrained PRF.

We propose online feedback path modeling with a pre-inverse type active noise control (PIANC) system to track the fluctuation stably in the feedback path. The conventional active noise control (ANC) system with online feedback path modeling (FBPM) filter bases filtered-x least mean square (FxLMS) algorithm. In the FxLMS algorithm, the error of FBPM influences a control filter, which generates an anti-noise, and secondary path modeling (SPM) filter. The control filter diverges when the error is too large. Therefore, it is difficult for the FxLMS algorithm to track the feedback path without divergence. On the other hand, the proposed approach converges stably because the FBPM filter's error does not influence a control filter on the PIANC system. Thus, the proposed method can reduce noise while tracking the feedback path. This paper verified the effectiveness of the proposed method by convergence analysis, computer simulation, and implementation of a digital signal processor.

Traffic categorization aims to classify network traffic into major service types. A modern deep neural network based on temporal sequence modeling is proposed for encrypted traffic categorization. The contemporary techniques such as dilated convolution and residual connection are adopted as the basic building block. The raw traffic files are pre-processed to generate 1-dimensional flow byte sequences and are feed into our specially-devised network. The proposed approach outperforms other existing methods greatly on a public traffic dataset.

In color image processing, preservation of hue is required. Therefore, perceptual color models such as HSI and HSV have been used. Hue-Saturation-Intensity (HSI) is a public color model, and many color applications have been made based on this model. However, the transformation from the conventional HSI (C-HSI) color space to the RGB color space after processing intensity/saturation in the C-HSI color space often generates the gamut problem, because the shape of C-HSI color space is a triangular pyramid which includes the RGB color space. When the output of intensity/saturation processing result is located in the outside of the common region of RGB color space and C-HSI color space, it is necessary to move to the RGB color space. The effective way of hue and intensity preserving saturation correction algorithm is proposed. According to the proposed saturation correction algorithm, the corrected saturation value is same as the processing result in the ideal HSI color space whose gamut same as the RGB gamut.

In network function virtualization (NFV) environments, service chaining is an emerging technology that enables network operators to provide network service dynamically and flexibly by using virtual network function (VNF). In the service chaining, a service chain is expected to be constructed based on VNF performances such as dependences among VNFs and traffic changing effects in VNFs. For achieving optimal data transmission services in NFV environments, we focus on the optimal service chain construction based on VNF performances so that both the maximum amount of traffic on links and the total number of VNF instances are decreased. In this paper, at first, an optimization problem is formulated for determining placements of VNFs and a route for each service chain. The service chains can be constructed by solving this optimization problem with an optimization software or meta-heuristic algorithm. Then, for the optimization problem, we propose a heuristic service chain construction algorithm. By using our proposed algorithm, the service chains can be constructed appropriately more quickly. We evaluate the performance of the proposed heuristic algorithm with simulation, and we investigate the effectiveness of the heuristic algorithm from the performance comparison. From some numerical examples, we show that the proposed heuristic algorithm is effective to decrease the amount of traffic and the number of VNF instances. Moreover, it is shown that our proposed heuristic algorithm can construct service chains quickly.

This paper reports the results of a new test on what types of failure cause falls in the stock prices of telecommunication service providers. This analysis of stock price is complementary to our previous one on market share. A clear result of our new test is that the type of failure causing falls in stock price is different from the type causing decline in market share. Specifically, the previous study identified frequent failures as causes of decline in market share, while the current study indicates large failures affecting many users as causes of falls in stock price. Together, these analyses give important information for reliability designs of telecommunications networks.

Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.

Convolutional neural networks (CNNs) have dominated a range of applications, from advanced manufacturing to autonomous cars. For energy cost-efficiency, developing low-power hardware for CNNs is a research trend. Due to the large input size, the first few convolutional layers generally consume most latency and hardware resources on hardware design. To address these challenges, this paper proposes an innovative architecture named SLIT to extract feature maps and reconstruct the first few layers on CNNs. In this reconstruction approach, total multiply-accumulate operations are eliminated on the first layers. We evaluate new topology with MNIST, CIFAR, SVHN, and ImageNet datasets on image classification application. Latency and hardware resources of the inference step are evaluated on the chip ZC7Z020-1CLG484C FPGA with Lenet-5 and VGG schemes. On the Lenet-5 scheme, our architecture reduces 39% of latency and 70% of hardware resources with a 0.456 W power consumption compared to previous works. Even though the VGG models perform with a 10% reduction in hardware resources and latency, we hope our overall results will potentially give a new impetus for future studies to reach a higher optimization on hardware design. Notably, the SLIT architecture efficiently merges with most popular CNNs at a slightly sacrificing accuracy of a factor of 0.27% on MNIST, ranging from 0.5% to 1.5% on CIFAR, approximately 2.2% on ImageNet, and remaining the same on SVHN databases.

This study proposes a design method for a rectifier circuit that can be rapidly charged by focusing on the design-load value of the circuit and the load fluctuation of a storage capacitor. The design-load value is suitable for rapidly charging the capacitor. It can be obtained at the lowest reflection condition and estimated according to the circuit design. This is a conventional method for designing the rectifier circuit using the optimum load. First, we designed rectifier circuits for the following three cases. The first circuit design uses a load set to 10 kΩ. The second design uses a load of 30 kΩ that is larger than the optimum load. The third design utilizes a load of 3 kΩ. Then, we measure the charging time to design the capacitor on each circuit. Consequently, the results show that the charge time could be shortened by employing the design-load value lower than that used in the conventional design. Finally, we discuss herein whether this design method can be applied regardless of the rectifier circuit topology.

Image dehazing is of great significance in computer vision and other fields. The performance of dehazing mainly relies on the precise computation of transmission map. However, the computation of the existing transmission map still does not work well in the sky area and is easily influenced by noise. Hence, the dark channel prior (DCP) and luminance model are used to estimate the coarse transmission in this work, which can deal with the problem of transmission estimation in the sky area. Then a novel weighted variational regularization model is proposed to refine the transmission. Specifically, the proposed model can simultaneously refine the transmittance and restore clear images, yielding a haze-free image. More importantly, the proposed model can preserve the important image details and suppress image noise in the dehazing process. In addition, a new Gaussian Adaptive Weighted function is defined to smooth the contextual areas while preserving the depth discontinuity edges. Experiments on real-world and synthetic images illustrate that our method has a rival advantage with the state-of-art algorithms in different hazy environments.

Most gait recognition approaches rely on silhouette-based representations due to high recognition accuracy and computational efficiency. A fundamental problem for those approaches is how to extract individuality-preserved silhouettes from real scenes accurately. Foreground colors may be similar to background colors, and the background is cluttered. Therefore, we propose a method of individuality-preserving silhouette extraction for gait recognition using standard gait models (SGMs) composed of clean silhouette sequences of various training subjects as shape priors. The SGMs are smoothly introduced into a well-established graph-cut segmentation framework. Experiments showed that the proposed method achieved better silhouette extraction accuracy by more than 2.3% than representative methods and better identification rate of gait recognition (improved by more than 11.0% at rank 20). Besides, to reduce the computation cost, we introduced approximation in the calculation of dynamic programming. As a result, without reducing the segmentation accuracy, we reduced 85.0% of the computational cost.

This paper presents a high jitter performance injection-locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100µW power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to minimize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO's flicker noise can be suppressed, and a good PN can be achieved in flicker region (1/f3) with sub-100µW power consumption. Thus, a high figure-of-merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5/-115.3dBc/Hz at 100kHz/1MHz frequency offset with a 97µW power consumption, which corresponds to a -193/-194dBc/Hz VCO FoM at 2.62GHz oscillation frequency. The measurement results show that the 1/f3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while using a high reference clock. A 960 fs RMS jitter can be achieved with a 40MHz common reference and 107µW corresponding power.

IoT devices operate with a battery and have embedded firmware in flash memory. If the embedded firmware is not kept up to date, there is a possibility of problems that cannot be linked with other IoT networks, so it is necessary to maintain the latest firmware with frequent updates. However, because firmware updates require developers and equipment, they consume manpower and time. Additionally, because the device must be active during the update, a low-power operation is not possible due to frequent flash memory access. In addition, if an unexpected interruption occurs during an update, the device is unavailable and requires a reliable update. Therefore, this paper aims to improve the reliability of updates and low-power operation by proposing a technique of performing firmware updates at high speed. In this paper, we propose a technique to update only a part of the firmware stored in nonvolatile flash memory without pre-processing to generate delta files. The firmware is divided into function blocks, and their addresses are collectively managed in a separate area called a function map. When updating the firmware, only the new function block to be updated is transmitted from the host downloader, and the bootloader proceeds with the update using the function block stored in the flash memory. Instead of transmitting the entire new firmware and writing it in the memory, using only function block reduces the amount of resources required for updating. Function-blocks can be called indirectly through a function map, so that the update can be completed by modifying only the function map regardless of the physical location. Our evaluation results show that the proposed technique effectively reduces the time cost, energy consumption, and additional memory usage overhead that can occur when updating firmware.

The performance of video action recognition has improved significantly in recent decades. Current recognition approaches mainly utilize convolutional neural networks to acquire video feature representations. In addition to the spatial information of video frames, temporal information such as motions and changes is important for recognizing videos. Therefore, the use of convolutions in a spatiotemporal three-dimensional (3D) space for representing spatiotemporal features has garnered significant attention. Herein, we introduce recent advances in 3D convolutions for video action recognition.

In this paper, we evaluate a prediction method of regions including dislocation clusters which are crystallographic defects in a photoluminescence (PL) image of multicrystalline silicon wafers. We applied a method of a transfer learning of the convolutional neural network to solve this task. For an input of a sub-region image of a whole PL image, the network outputs the dislocation cluster regions are included in the upper wafer image or not. A network learned using image in lower wafers of the bottom of dislocation clusters as positive examples. We experimented under three conditions as negative examples; image of some depth wafer, randomly selected images, and both images. We examined performances of accuracies and Youden's J statistics under 2 cases; predictions of occurrences of dislocation clusters at 10 upper wafer or 20 upper wafer. Results present that values of accuracies and values of Youden's J are not so high, but they are higher results than ones of bag of features (visual words) method. For our purpose to find occurrences dislocation clusters in upper wafers from the input wafer, we obtained results that randomly select condition as negative examples is appropriate for 10 upper wafers prediction, since its results are better than other negative examples conditions, consistently.

We previously developed a new terahertz (THz) wave detection method that utilizes the effect of nonlinear optical (NLO) polymers. The new method provided us with a gapless detection, a wide detection bandwidth, and a simpler optical geometry in the THz wave detection. In this paper, polarization dependences in THz wave detection by the Stark effect were investigated. The projection model was employed to analyze the polarization dependences and the consistency with experiments was observed qualitatively, surely supporting the use of the first-order Stark effect in this method. The relations between THz wave detection by the Stark effect and Stark spectroscopy or electroabsorption spectroscopy are also discussed.

In this paper, we explore the physical layer security of an Internet of Things (IoT) network comprised of multiple relay-user pairs in the presence of multiple malicious eavesdroppers and channel estimation error (CEE). In order to guarantee secure transmission with channel estimation error, we propose a channel estimation error oriented joint relay-user pair and friendly jammer selection (CEE-JRUPaFJS) scheme to improve the physical layer security of IoT networks. For the purpose of comparison, the channel estimation error oriented traditional round-robin (CEE-TRR) scheme and the channel estimation error oriented traditional pure relay-user pair selection (CEE-TPRUPS) scheme are considered as benchmark schemes. The exact closed-form expressions of outage probability (OP) and intercept probability (IP) for the CEE-TRR and CEE-TPRUPS schemes as well as the CEE-JRUPaFJS scheme are derived over Rayleigh fading channels, which are employed to characterize network reliability and security, respectively. Moreover, the security-reliability tradeoff (SRT) is analyzed as a metric to evaluate the tradeoff performance of CEE-JRUPaFJS scheme. It is verified that the proposed CEE-JRUPaFJS scheme is superior to both the CEE-TRR and CEE-TPRUPS schemes in terms of SRT, which demonstrates our proposed CEE-JRUPaFJS scheme are capable of improving the security and reliability performance of IoT networks in the face of multiple eavesdroppers. Moreover, as the number of relay-user pairs increases, CEE-TPRUPS and CEE-JRUPaFJS schemes offer significant increases in SRT. Conversely, with an increasing number of eavesdroppers, the SRT of all these three schemes become worse.

Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse-Grained Reconfigurable Arrays (CGRAs) have received attention because of their high energy efficiency. For further reduction of the standby energy consumption of CGRAs, the leakage power for their configuration memory must be reduced. Although the power gating is a common technique, the lost data in flip-flops and memory must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Next, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the average availability ratio of 94.2% was achieved, while the average availability ratio of the nine applications was 0.056% when the probability of failure of the FF was 0.01. The energy for storing data becomes about 2.3 times because of the hardware overhead of ECC but the proposed method can save 8.6% of the writing power on average.

Since most sensor data depend on each other, time-series anomaly detection is one of practical applications of IoT devices. Such tasks are handled by Recurrent Neural Networks (RNNs) with a feedback structure, such as Long Short Term Memory. However, their learning phase based on Stochastic Gradient Descent (SGD) is computationally expensive for such edge devices. This issue is addressed by executing their learning on high-performance server machines, but it introduces a communication overhead and additional power consumption. On the other hand, Recursive Least-Squares Echo State Network (RLS-ESN) is a simple RNN that can be trained at low cost using the least-squares method rather than SGD. In this paper, we propose its area-efficient hardware implementation for edge devices and adapt it to human activity anomaly detection as an example of interdependent time-series sensor data. The model is implemented in Verilog HDL, synthesized with a 45 nm process technology, and evaluated in terms of the anomaly capability, hardware amount, and performance. The evaluation results demonstrate that the RLS-ESN core with a feedback structure is more robust to hyper parameters than an existing Online Sequential Extreme Learning Machine (OS-ELM) core. It consumes only 1.25 times larger hardware amount and 1.11 times longer latency than the existing OS-ELM core.

Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.