In December 2018, satellite broadcasting for 4K/8K ultra-high-definition television (UHDTV) will begin in Japan. It will be provided in the 12-GHz (11.7 to 12.75GHz) band with right- and left-hand circular polarizations. BSAT-4a, a satellite used for broadcasting UHDTV, was successfully launched in September 2017. This satellite has not only 12-GHz-band right- and left-hand circular polarization transponders but also a 21-GHz-band experimental transponder. The 21-GHz (21.4 to 22.0GHz) band has been allocated as the downlink for broadcasting satellite service in ITU-R Regions 1 (Europe, Africa) and 3 (Asia Pacific). To receive services provided over these two frequency bands and with dual-polarization, we implement and evaluated a dual-band and dual-circularly polarized parabolic reflector antenna fed by 12- and 21-GHz-band microstrip antenna arrays with a multilayer structure. The antenna is used to receive 12- and 21-GHz-band signals from in-orbit satellites. The measured and experimental results prove that the proposed antenna performs as a dual-polarized antenna in those two frequency bands and has sufficient performance to receive satellite broadcasts.

In this paper, a high-frequency resolution Digital Frequency Discriminator (DFD) IC using a Time to Digital Converter (TDC) and an edge counter for Instantaneous Frequency Measurement (IFM) is proposed. In the proposed DFD, the TDC measures the time of the maximum periods of divided RF short pulse signals, and the edge counter counts the maximum number of periods of the signal. By measuring the multiple periods with the TDC and the edge counter, the proposed DFD improves the frequency resolution compared with that of the measuring one period because it is proportional to reciprocal of the measurement time of TDC. The DFD was fabricated using 0.18-um SiGe-BiCMOS. Frequency accuracy below 0.39MHz and frequency precision below 1.58 MHz-RMS were achieved during 50 ns detection time in 0.3 GHz to 5.5 GHz band with the temperature range from -40 to 85 degrees.

A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.

The symbol flipping decoding algorithms based on prediction (SFDP) for non-binary LDPC codes perform well in terms of error performances but converge slowly when compared to other symbol flipping decoding algorithms. In order to improve the convergence rate, we design new flipping rules with two phases for the SFDP algorithms. In the first phase, two or more symbols are flipped at each iteration to allow a quick increase of the objective function. While in the second phase, only one symbol is flipped to avoid the oscillation of the decoder when the objective function is close to its maximum. Simulation results show that the SFDP algorithms with the proposed flipping rules can reduce the average number of iterations significantly, whereas having similar performances when compared to the original SFDP algorithms.

Wireless communication security has been increasingly important nowadays. Directional modulation (DM) is seen as a promising wireless physical layer security technology. Traditional DM is a transmit-side technology that projects digitally modulated information signals in the desired directions (or at the desired locations) while simultaneously distorting the constellation formats of the same signals in other directions (or at all other locations). However, these directly exposed digitally modulated information signals are easily intercepted by eavesdroppers along the desired directions (or around the desired locations). A new DM scheme for secure point-to-multipoint communication based on the spread spectrum assisted orthogonal frequency diverse array (short for SS-OFDA-M-DM) is proposed in this paper. It can achieve point-to-multipoint secure communication for multiple cooperative receivers at different locations. In the proposed SS-OFDA-M-DM scheme, only cooperative users that use specific DM receivers with right spread spectrum parameters can retrieve right symbols. Eavesdroppers without knowledge of spread spectrum parameters cannot intercept useful signals directly at the desired locations. Moreover, they cannot receive normal symbols at other locations either even if the right spread spectrum parameters are known. Numerical simulation results verify the validity of our proposed scheme.

We numerically demonstrate a possibility on-off keying (OOK) type of modulation over tens gigabits per second for sub-terahertz radiation in our proposed wireless transmitter device structure towards radio over fiber (RoF) technology. The integrated device consists of an InP-based compound semiconductor resonant tunneling diode (RTD) adjacent to an InP-based photo diode (PD), a self-complementary type of bow-tie antenna (BTA), external microstrip lines. These integration structures are carefully designed to obtain robust relaxation oscillation (RO) due to the negative differential conductance (NDC) characteristic of the RTD and the nonlinearity of the NDC. Moreover, the device is designed to exhibit OOK modulation of RO due to photo current from the PD inject into the RTD. Electromagnetic simulations and nonlinear equivalent circuit model of the whole device structure are established to perform large signal analysis numerically with considerations of previously measured characteristics of the triple-barrier RTD.

It has been reported repeatedly that discriminative learning of distance metric boosts the pattern recognition performance. Although the ITML (Information Theoretic Metric Learning)-based methods enjoy an advantage that the Bregman projection framework can be applied for optimization of distance metric, a weak point of ITML-based methods is that the distance threshold for similarity/dissimilarity constraints must be determined manually, onto which the generalization performance is sensitive. In this paper, we present a new formulation of metric learning algorithm in which the distance threshold is optimized together. Since the optimization is still in the Bregman projection framework, the Dykstra algorithm can be applied for optimization. A nonlinear equation has to be solved to project the solution onto a half-space in each iteration. We have developed an efficient technique for projection onto a half-space. We empirically show that although the distance threshold is automatically tuned for the proposed metric learning algorithm, the accuracy of pattern recognition for the proposed algorithm is comparable, if not better, to the existing metric learning methods.

We have fabricated multiple-stacked Si quantum dots (QDs) with and without Ge core embedded in a SiO2 network on n-Si(100) and studied their field electron emission characteristics under DC bias application. For the case of pure Si-QD stacks with different dot-stack numbers, the average electric field in dot-stacked structures at which electron emission current appeared reached minimum value at a stack number of 11. This can be attributed to optimization of the electron emission due to enhanced electric field concentration in the upper layers of the dot-stacked structures and reduction of the electron injection current from the n-Si substrate, with an increased stack number. We also found that, by introducing Ge core into Si-QDs, the average electric field for the electron emission can be reduced below that from pure Si-QDs-stacked structures. This result implies that the electric field is more concentrated in the upper Si-QDs with Ge core layers due to deep potential well for holes in the Ge core.

A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.

To expand the use of systems using a camera on portable devices such as tablets and smartphones, we have developed and propose a memory saving feature descriptor, the use of which is one of the essential techniques in computer vision. The proposed descriptor compares pixel values of pre-fixed positions in the small patch around the feature point and stores binary values. Like the conventional descriptors, it extracts the patch on the basis of the scale and orientation of the feature point. For memories of the same size, it achieves higher accuracy than ORB and BRISK in all cases and AKAZE for the images with textured regions.

An optimized low-power optical memory access network is proposed to alleviate the cost of microring resonators (MRs) in kilocore systems, such as the pass-by loss and integration difficulty. Compared with traditional electronic bus interconnect, the proposed network reduces power consumption and latency by 80% to 89% and 21% to 24%. Moreover, the new network decreases the number of MRs by 90.6% without an increase in power consumption and latency when making a comparison with Optical Ring Network-on-Chip (ORNoC).

This paper presents a theoretical analysis and experimental confirmation of a tunable ring resonator that can independently change its resonant frequency and bandwidth. The tunable ring resonator comprises a ring resonator, three tunable capacitors, and switches. The resonant frequency changes according to the capacitance of tunable capacitors, and the bandwidth varies by changing the state of the switches. The unique feature of the resonator is that the resonant frequency remains steady when the bandwidth is changed. The fundamental characteristics are shown based on linear circuit simulation and electromagnetic simulation results. The resonator is fabricated using GaAs FET single-pole single-throw switches. The fabricated resonator changes the resonant frequency from 1.5 GHz to 2.0 GHz and the fractional bandwidth from 5% to 30%.

Since the hardware resource of a single FPGA is limited, one idea to scale the performance of FPGA-based HPC applications is to expand the design space with multiple FPGAs. This paper presents a scalable architecture of a deeply pipelined stream computing platform, where available parallelism and inter-FPGA link characteristics are investigated to achieve a scaled performance. For a practical exploration of this vast design space, a performance model is presented and verified with the evaluation of a tsunami simulation application implemented on Intel Arria 10 FPGAs. Finally, scalability analysis is performed, where speedup is achieved when increasing the computing pipeline over multiple FPGAs while maintaining the problem size of computation. Performance is scaled with multiple FPGAs; however, performance degradation occurs with insufficient available bandwidth and large pipeline overhead brought by inadequate data stream size. Tsunami simulation results show that the highest scaled performance for 8 cascaded Arria 10 FPGAs is achieved with a single pipeline of 5 stream processing elements (SPEs), which obtained a scaled performance of 2.5 TFlops and a parallel efficiency of 98%, indicating the strong scalability of the multi-FPGA stream computing platform.

In this paper, we propose a method for automatic virtual resource allocation by using a multi-target classification-based scheme (MTCAS). In our method, an Infrastructure Provider (InP) bundles its CPU, memory, storage, and bandwidth resources as Network Elements (NEs) and categorizes them into several types in accordance to their function, capabilities, location, energy consumption, price, etc. MTCAS is used by the InP to optimally allocate a set of NEs to a Virtual Network Operator (VNO). Such NEs will be subject to some constraints, such as the avoidance of resource over-allocation and the satisfaction of multiple Quality of Service (QoS) metrics. In order to achieve a comparable or higher prediction accuracy by using less training time than the available ensemble-based multi-target classification (MTC) algorithms, we propose a majority-voting based ensemble algorithm (MVEN) for MTCAS. We numerically evaluate the performance of MTCAS by using the MVEN and available MTC algorithms with synthetic training datasets. The results indicate that the MVEN algorithm requires 70% less training time but achieves the same accuracy as the related ensemble based MTC algorithms. The results also demonstrate that increasing the amount of training data increases the efficacy ofMTCAS, thus reducing CPU and memory allocation by about 33% and 51%, respectively.

Soft error jeopardizes the reliability of semiconductor devices, especially those working at low voltage. In recent years, silicon-on-thin-box (SOTB), which is a FD-SOI device, is drawing attention since it is suitable for ultra-low-voltage operation. This work evaluates the contributions of SRAM, FF and combinational circuit to chip-level soft error rate (SER) based on irradiation test results. For this evaluation, this work performed neutron irradiation test for characterizing single event transient (SET) rate of SOTB and bulk circuits at 0.5 V. Using the SBU and MCU data in SRAMs from previous work, we calculated the MBU rate with/without error correcting code (ECC) and with 1/2/4-col MUX interleaving. Combining FF error rates reported in literature, we estimated chip-level SER and each contribution to chip-level SER for embedded and high-performance processors. For both the processors, without ECC, 95% errors occur at SRAM in both SOTB and bulk chips at 0.5 V and 1.0 V, and the overall chip-level SERs of the assumed SOTB chip at 0.5 V is at least 10 x lower than that of bulk chip. On the other hand, when ECC is applied to SRAM in the SOTB chip, SEUs occurring at FFs are dominant in the high-performance processor while MBUs at SRAMs are not negligible in the bulk embedded chips.

We report our recent progress in silicon photonics integrated device technology targeting on-chip-level large-capacity optical interconnect applications. To realize high-capacity data transmission, we successfully developed on-package-type silicon photonics integrated transceivers and demonstrated simultaneous 400 Gbps operation. 56 Gbps pulse-amplitude-modulation (PAM) 4 and wavelength-division-multiplexing technologies were also introduced to enhance the transmission capacity.

In super-Nyquist wavelength division multiplexed systems, performance of forward error correction (FEC) can be improved by an iterative decoder between a maximum likelihood decoder for polybinary shaping and an FEC decoder. The typical iterative decoder includes not only the iteration between the first and second decoders but also the internal iteration within the FEC decoder. Such two-fold loop configuration would increase the computational complexity for decoding. In this paper, we propose the simplified iterative decoder, where the internal iteration in the FEC decoder is not performed, reducing the computational complexity. We numerically evaluate the bit-error rate performance of polybinary-shaped QPSK signals in the simplified iterative decoder. The numerical results show that the FEC performance can be improved in the simplified scheme, compared with the typical iterative decoder. In addition, the performance of the simplified iterative decoder has been investigated by the extrinsic information transfer (EXIT) chart.

The recent widespread use of high-performance terminals has resulted in a rapid increase in mobile data traffic. Therefore, public wireless local area networks (WLANs) are being used often to supplement the cellular networks. Capacity improvement through the dense deployment of access points (APs) is being considered. However, the effective throughput degrades significantly when many users connect to a single AP. In this paper, users are classified into guaranteed bit rate (GBR) users and best effort (BE) users, and we propose a network model to provide those services. In the proposed model, physical APs and the bandwidths are assigned to each service class dynamically using a virtual AP configuration and a virtualized backhaul network, for reducing the call-blocking probability of GBR users and improving the satisfaction degree of BE users. Finally, we evaluate the performance of the proposed model through simulation experiments and discuss its feasibility.

This paper proposes a low-profile unidirectional supergain antenna applicable to wireless communication devices such as mobile terminals, the Internet of Things and so on. The antennas used for such systems are required to be not only electrically low-profile but also unsusceptible to surrounding objects such as human body and/or electrical equipment. The proposed antenna achieves both requirements due to its supergain property using planar elements and a closely placed planar reflector. The primary antenna is an asymmetric dipole type, and consists of a monopole element mounted on an edge of a rectangular conducting plane. Both elements are placed on a dielectric substrate backed by the planar reflector. It is numerically and experimentally shown that the supergain property is achieved by optimizing the geometrical parameters of the antenna. It is also shown that the impedance characteristics can be successfully adjusted by changing the lengths of the ground plane element and the monopole element. Thus, no additional impedance matching circuit is necessary. Furthermore, it is shown that surrounding objects have insignificant impact on the antenna performance.

With the spread of map applications, route generation has become a familiar function. Most of route generation methods search a route from a starting point to a destination point with the shortest time or shortest length, but more enjoyable route generation is recently focused on. Particularly, cyclic-route generation for strolling requires to suggest to a user more than one route passing through several POIs (Point-of-Interests), to satisfy the user's preferences as much as possible. In this paper, we propose a multiple cyclic-route generation method with a route length constraint considering POIs. Firstly, our proposed method finds out a set of reference points based on the route length constraint. Secondly, we search a non-cyclic route from one reference point to the next one and finally generate a cyclic route by connecting these non-cyclic routes. Compared with previous methods, our proposed method generates a cyclic route closer to the route length constraint, reduces the number of the same points passing through by approximately 80%, and increases the number of POIs passed approximately 1.49 times.