A rectifying antenna is one of the most important components for wireless power transmission applications. In our previous papers, some RF-DC conversion circuits with high conversion efficiency at low input power are proposed. However, these RF-DC conversion circuits have some parts of which size depends on operating frequency, so the circuit size becomes large at low operating frequency. And, the composition of these RF-DC conversion circuits is complicated. Therefore, in this paper, a new RF-DC conversion circuit composed of only chip devices is proposed. This circuit has higher conversion efficiency than the previously proposed circuits. And, size reduction of the RF-DC conversion circuit is realized. Moreover, the composition of the circuit is simple, so the circuit size does not depend on operating frequency. For design of the RF-DC conversion circuits, LE-FDTD method is used. The measurement results agree with analytical results of the LE-FDTD method very well, and availability of the LE-FDTD method is discovered. It is shown that LE-FDTD method is a powerful analytical way which can give efficient design of RF-DC conversion circuit with high conversion efficiency.

Drain collapse in AlGaN/GaN HFET is analyzed using a two-dimensional device simulator. Two-step saturation is obtained, assuming hole-trap type surface states on the AlGaN surface and a short negative-charge-injected region at the drain side of the gate. Due to the surface electric potential pinning by the surface traps, the negative charge injected region forms a constant potential like in a metal gate region and it acts as an FET with a virtual gate. The electron concentration profile reveals that the first saturation occurs by pinch-off in the virtual gate region and the second saturation occurs by the pinch-off in the metal gate region. Due to the short-channel effect of the virtual gate FET, the saturation current increases until it finally reaches the saturation current of the intrinsic metal gate FET. Current collapses with current degradation at the knee voltage in the I-V characteristics can be explained by the formation of the virtual gate.

DTDs are continuously updated according to changes in the real world. Let t be an XML document valid against a DTD D, and suppose that D is updated by an update script s. In general, we cannot uniquely "infer" a transformation of t from s, i.e., we cannot uniquely determine the elements in t that should be deleted and/or the positions in t that new elements should be inserted into. In this paper, we consider inferring K optimum transformations of t from s so that a user finds the most desirable transformation more easily. We first show that the problem of inferring K optimum transformations of an XML document from an update script is NP-hard even if K = 1. Then, assuming that an update script is of length one, we show an algorithm for solving the problem, which runs in time polynomial of |D|, |t|, and K.

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.

Method for eliminating magnetic saturation in low-voltage and high-current DC-DC converter with fast dynamic response is described. The magnetic saturation is observed in onboard isolated bridge-type DC-DC converter due to inherently asymmetrical PWM signal during transient condition. The saturation is not eliminated by using ac-coupling capacitor for transformer. Mechanism of the saturation is analyzed and confirmed by experiments. Based on the analysis a solution for the magnetic saturation is proposed. The effectiveness of proposed method is also confirmed by experiments.

Digital signal processing requires digital filters with variable frequency characteristics. A variable digital filter (VDF) is a filter whose frequency characteristics can be easily and instantaneously changed. In this paper, we present a design method for variable linear-phase finite impulse response (FIR) filters with multiple variable factors and a reduction method for the number of polynomial coefficients. The obtained filter has a high piecewise attenuation in the stopband. The stopband edge and the position and magnitude of the high piecewise stopband attenuation can be varied by changing some parameters. Variable parameters are normalized in this paper. An optimization methodology known as semidefinite programming (SDP) is used to design the filter. In addition, we present that the proposed VDF can be implemented using the Farrow structure, which suitable for real time signal processing. The usefulness of the proposed filter is demonstrated through examples.

To improve the high voltage performance of AlGaN/GaN heterojunction field effect transistors (HFETs), we have fabricated AlGaN/GaN HFETs with p-GaN epi-layer on sapphire substrate with an ohmic contact to the p-GaN (p-sub HFET). Substrate bias dependent threshold voltage variation (VT-VSUB) was used to directly determine the doping concentration profile in the buffer layer. This VT-VSUB method was developed from Si MOSFET. For HFETs, the insulator is formed by epitaxially grown and heterogeneous semiconductor layer while for Si MOSFETs the insulator is amorphous SiO2. Except that HFETs have higher channel mobility due to the epitaxial insulator/semiconductor interface, HFETs and Si MOSFETs are basically the same in the respect of device physics. Based on these considerations, the feasibility of this VT-VSUB method for AlGaN/GaN HFETs was discussed. In the end, the buffer layer doping concentration was measured to be 21017 cm-3, p-type, which is well consistent with the Mg concentration obtained from secondary ion mass spectroscopy (SIMS) measurement.

In this study, we construct an analytical model to investigate the system throughput of 802.15.3c WPAN by examining hybrid slotted CSMA/CA-TDMA and slotted CSMA/CA multiple access methods. Our analysis clearly shows the differences between the system throughputs of both multiple access methods. The obtained results show that the hybrid slotted CSMA/CA-TDMA can achieve a considerably higher system throughput compared to the slotted CSMA/CA; the difference between the two access methods is especially pronounced as the increase in the number of devices contending for the network increase. The system throughput comparisons have established why the hybrid slotted CSMA/CA-TDMA is preferred over the slotted CSMA/CA for high-speed wireless communications of the 802.15.3c WPAN.

Motivated by the needs of modern agriculture, in this paper we present CropNET, a wireless multimedia sensor network system for agriculture monitoring. Both hardware and software designs of CropNET are tailored for sensing in wide farmland without human supervision. We have carried out multiple rounds of deployments. The evaluation results show that CropNET performs well and facilitates modern agriculture.

In this letter, we develop a behavioral metric with which spamming botnets can be quickly identified with respect to their residing IP blocks. Our method aims at line-speed operation without deep inspection, so only TCP/IP header fields of the passing packets are examined. However, the proposed metric yields a high-quality receiver operating characteristics (ROC), with high detection rates and low false positive rates.

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.

Novel thermopiles based on modulation doped AlGaAs/InGaAs, AlGaN/GaN, and ZnMgO/ZnO heterostructures are proposed and designed for the first time, for uncooled infrared image sensor application. These devices are expected to offer high performances due to both the superior Seebeck coefficient and the excellently high mobility of 2DEG and 2DHG due to high purity channel layers at the heterojunction interface. The AlGaAs/InGaAs thermopile has the figure-of-merit Z of as large as 1.110-2/K (ZT = 3.3 over unity at T = 300 K), and can be realized with a high responsivity R of 15,200 V/W and a high detectivity D* of 1.8109 cmHz1/2/W with uncooled low-cost potentiality. The AlGaN/GaN and the ZnMgO/ZnO thermopiles have the advantages of high sheet carrier concentration due to their large polarization charge effects (spontaneous and piezo polarization charges) as well as of a high Seebeck coefficient due to their strong phonon-drag effect. The high speed response time τ of 0.9 ms with AlGaN/GaN, and also the lower cost with ZnMgO/ZnO thermopiles can be realized. The modulation-doped heterostructure thermopiles presented here are expected to be used for uncooled infrared image sensor applications, and for monolithic integrations with other photon detectors such as InGaAs, GaN, and ZnO PiN photodiodes, as well as HEMT functional integrated circuit devices.

In this letter, we propose a low-complexity sparse channel estimation method for orthogonal frequency division multiplexing (OFDM) systems. The proposed method uses a discrete Fourier transform (DFT)-based technique for channel estimation and a novel sorted noise space discrimination technique to estimate the channel length and tap positions. Simulation results demonstrate that the reduction in signal space improves the channel estimation performance.

In this letter, we present a real-time orientation estimation and motion tracking scheme using interacting multiple model (IMM) based Kalman filtering method. Two nonlinear filters, quaternion-based extended Kalman filter (QBEKF) and gyroscope-based extended Kalman filter (GBEKF) are utilized in the proposed IMM-based orientation estimator for sensor motion state estimation. In the QBEKF, measurements from gyroscope, accelerometer and magnetometer are processed; while in the GBEKF, sole measurements from gyroscope are processed. The interacting multiple model algorithm is used for fusing the estimated states via adaptive model weighting. Simulation results validate the proposed design concept, and the scheme is capable of reducing overall estimation errors in sensor motion tracking.

We theoretically study the performance limits of current-gain cutoff frequency, fT, for the HEMTs with InAs or In0.70Ga0.30As middle layers in the multi-quantum-well (MQW) channels by means of the quantum-corrected Monte Carlo (MC) method. We calculate the distribution of the delay time along the channel, τ(x), and define the effective gate length, Lg,eff, as the corresponding length to τ(x). By extrapolating Lg,eff to Lg = 0 nm, we estimate the lower limit of Lg,eff, Lg(0),eff. Then we estimate the performance limit of fT, fT(0), by extrapolating fT to Lg,eff(0). The estimated fT(0) are about 3.6 and 3.7 THz for the HEMTs with InAs middle layers of 5 and 8 nm in thickness, and about 3.0 THz for the HEMT with In0.70Ga0.30As middle layer of 8 nm in thickness, respectively. The higher fT(0) in the HEMTs with InAs middle layers are attributed to the increased average electron velocity, υd, in the channel. These results indicate the superior potential of the HEMTs using InAs in the channels. The HEMT with InAs middle layer of 8 nm in thickness shows the highest fT on condition of the same Lg because of its highest υd. However, the increased total channel thickness results in the longer Lg,eff(0), which leads to the restriction of fT(0). Therefore, in order to increase fT(0), it is essential to make Lg,eff short in addition to making υd high. Our results strongly encourage in making an effort to develop the HEMTs that operate in the terahertz region.

We propose a low-power eFuse one-time programmable (OTP) memory IP based on a bipolar CMOS DMOS (BCD) process. It is an eFuse OTP memory cell which uses separate transistors that are optimized in program and in read mode. The eFuse cell also uses poly-silicon gates having co-silicide. An asynchronous interface and a separate I/O method are used for the low-power and small-area eFuse OTP memory IP. Additionally, we propose a new circuit protecting a short-circuit current in the VDD-to-VIO voltage level translator circuit while the VDD voltage is being generated by the voltage regulator at power-up. A digital sensing circuit using clocked inverters is used to sense a bit-line (BL) datum. Furthermore, the poly-silicon of the IP is split into n+ poly-silicon and p+ poly-silicon to optimize the eFuse link. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18 µm BCD process is 283.565524.180 µm2. It is measured by manufactured test IPs with Dongbu HiTek's 0.18 µm BCD process that the programming voltage of the n+ gate poly-silicon is about 0.1 V less than that of the p+ gate poly-silicon.

The error diffusion filter in this paper is optimized with respect to the ideal blue noise pattern corresponding to a single tone level. The filter coefficients are optimized by the minimization of the squared error norm between the Fourier power spectra of the resulting halftone and the blue noise pattern. During the process of optimization, the binary pattern power spectrum matching algorithm is applied with the aid of a new blue noise model. The number of the optimum filters is equal to that of different tones. The visual fidelity of the bilevel halftones generated by the error diffusion filters is evaluated in terms of a weighted signal-to-noise ratio, Fourier power spectra, and others. Experimental results have demonstrated that the proposed filter set generates satisfactory bilevel halftones of grayscale images.

This paper proposes two novel frame resource allocation schemes: Mixed bidirectional allocation scheme and Offset allocation scheme. They improve system capacity and latency performance unlike the conventional time-division duplex relay scheme which divides the frame structure into time segments for the access zone and time segment for the relay zones as in IEEE802.16j (WiMAX) systems. Computer simulations confirm that the two proposed schemes outperform the conventional schemes in terms of throughput and latency. An evaluation of the offset allocation scheme confirms that it improves the total throughput by about 85%, and reduces latency by about 72%, compared to the conventional schemes.

This paper proposes an interference avoidance technique that allows wireless device with similar frequency bands to be operated adjacent to each other for compact mobile wireless routers (MWRs). This MWR implements two devices of Wireless LAN (WLAN) and Worldwide Interoperability for Microwave Access (WiMAX). The MWR connects WLAN terminals to the backbone network by using WiMAX-WLAN relay. Generally, different frequency channels are assigned for the wireless systems assign in order not to interfere among multiple systems. However, mutual system interference is generated if the space between each device is very close and if the frequency using each system is adjacent. To suppress this interference, this paper proposes a novel interference avoidance technique that leverages IEEE802.11n Power Save Multi-Poll (PSMP). First, we clarify the conditions that raise the issues of mutual interference by experiment. Simulations are conducted to show that the proposed scheme outperforms the conventional schemes. Finally, the effectiveness of the proposed scheme is shown by the computer simulation.

In this paper, a coexistence mechanism between IEEE 802.15.4 and IEEE 802.11b, Active Channel Reservation for cOexiStence (ACROS), is proposed. The key idea underlining ACROS is to reserve the channel for IEEE 802.15.4 transmission, where IEEE 802.11 transmissions are forbidden. The request-to-send (RTS)/clear-to send (CTS) mechanism within IEEE 802.11 is used to reserve a channel. The proposed ACROS mechanism is implemented into a PC based prototype. The embedded version of ACROS is also developed to mitigate the timing drift problem in the PC-based ACROS. The efficiency of ACROS is shown using the throughput and packet error rate achieved in actual experiments.