Novel thermopiles based on modulation doped AlGaAs/InGaAs, AlGaN/GaN, and ZnMgO/ZnO heterostructures are proposed and designed for the first time, for uncooled infrared image sensor application. These devices are expected to offer high performances due to both the superior Seebeck coefficient and the excellently high mobility of 2DEG and 2DHG due to high purity channel layers at the heterojunction interface. The AlGaAs/InGaAs thermopile has the figure-of-merit Z of as large as 1.110-2/K (ZT = 3.3 over unity at T = 300 K), and can be realized with a high responsivity R of 15,200 V/W and a high detectivity D* of 1.8109 cmHz1/2/W with uncooled low-cost potentiality. The AlGaN/GaN and the ZnMgO/ZnO thermopiles have the advantages of high sheet carrier concentration due to their large polarization charge effects (spontaneous and piezo polarization charges) as well as of a high Seebeck coefficient due to their strong phonon-drag effect. The high speed response time τ of 0.9 ms with AlGaN/GaN, and also the lower cost with ZnMgO/ZnO thermopiles can be realized. The modulation-doped heterostructure thermopiles presented here are expected to be used for uncooled infrared image sensor applications, and for monolithic integrations with other photon detectors such as InGaAs, GaN, and ZnO PiN photodiodes, as well as HEMT functional integrated circuit devices.

In this letter, we propose a low-complexity sparse channel estimation method for orthogonal frequency division multiplexing (OFDM) systems. The proposed method uses a discrete Fourier transform (DFT)-based technique for channel estimation and a novel sorted noise space discrimination technique to estimate the channel length and tap positions. Simulation results demonstrate that the reduction in signal space improves the channel estimation performance.

Higher frame-rates are essential in achieving more realistic representations. Since increasing the frame-rate increases the total amount of information, efficient coding methods are required. However, the statistical properties of such data, needed for designing sufficiently powerful encoders, have not been clarified. Conventional studies on encoding high frame-rate sequences do not consider the effect on the encoding bit-rate of the motion blur generated by the shutter being open. When the open interval of the shutter in the image pickup apparatus increases, motion blur occurs, which is known as the integral phenomenon. The integral phenomenon changes the statistical properties of the video signal. This paper derives, for high frame-rate video, a mathematical model that quantifies the relationship between frame-rate and bit-rate; it incorporates the effect of the low-pass filtering induced by the open shutter. A coding experiment confirms the validity of the mathematical model.

There has been much interest in a spatial query which acquires sensor readings from sensor nodes inside specified geographical area of interests. A centralized approach performs the spatial query at a server after acquiring all sensor readings. However, it incurs high wireless transmission cost in accessing all sensor nodes. Therefore, various in-network spatial search methods have been proposed, which focus on reducing the wireless transmission cost. However, the in-network methods sometimes incur unnecessary wireless transmissions because of dead space, which is spatially indexed but does not contain real data. In this paper, we propose a hybrid spatial query processing algorithm which removes the unnecessary wireless transmissions. The main idea of the hybrid algorithm is to find results of a spatial query at a server in advance and use the results in removing the unnecessary wireless transmissions at a sensor network. We compare the in-network method through several experiments and clarify our algorithm's remarkable features.

In speech recognition, confidence annotation adopts a single confidence feature or a combination of different features for classification. These confidence features are always extracted from decoding information. However, it is proved that about 30% of knowledge of human speech understanding is mainly derived from high-level information. Thus, how to extract a high-level confidence feature statistically independent of decoding information is worth researching in speech recognition. In this paper, a novel confidence feature extraction algorithm based on latent topic similarity is proposed. Each word topic distribution and context topic distribution in one recognition result is firstly obtained using the latent Dirichlet allocation (LDA) topic model, and then, the proposed word confidence feature is extracted by determining the similarities between these two topic distributions. The experiments show that the proposed feature increases the number of information sources of confidence features with a good information complementary effect and can effectively improve the performance of confidence annotation combined with confidence features from decoding information.

This paper proposes a new multi-band received signal strength (MRSS) fingerprinting based indoor location system, which employs the frequency diversity on the conventional single-band received signal strength (RSS) fingerprinting based indoor location system. In the proposed system, the impacts of frequency diversity on the enhancements of positioning accuracy are analyzed. Effectiveness of the proposed system is proved by experimental approach, which was conducted in non line-of-sight (NLOS) environment under the area of 103 m2 at Yagami Campus, Keio University. WLAN access points, which simultaneously transmit dual-band signal of 2.4 and 5.2 GHz, are utilized as transmitters. Likewise, a dual-band WLAN receiver is utilized as a receiver. Signal distances calculated by both Manhattan and Euclidean were classified by K-Nearest Neighbor (KNN) classifier to illustrate the performance of the proposed system. The results confirmed that Frequency diversity attributions of multi-band signal provide accuracy improvement over 50% of the conventional single-band.

Conventional RFID interrogators use symbol-by-symbol-based detectors such as the matched filter and the edge detector for signal detection which do not sufficiently exploit the structure of the data-encoded waveforms. In this paper we propose a Viterbi-based algorithm to detect the data sequence of the RFID systems using the EPC-Global Generation-2 standard. By decomposing the associated data-encoded waveform on a half-cycle basis, the proposed approach first transfer the representation of the data-encoding scheme to a trellis diagram and thus leads to the application of the Viterbi algorithm for data sequence estimation. Also, different from the traditional Viterbi algorithm using correlation coefficient as the branch metrics, the proposed algorithm uses the absolute correlation coefficient as our branch metric which can exactly save the computational complexity of the Viterbi algorithm up to 50 percent. As compared to conventional approaches, the proposed algorithm can significantly improve the system performance due to its full exploitation of the baseband signal structure.

This paper presents a paraunitary filter bank (PUFB) based on a direct lifting structure of a building block and its inverse transform for lossless-to-lossy image coding. Although the conventional lifting-based filter banks (LBFBs), which are constructed by lifting structures with integer coefficients and rounding operations, suffer from degradation of coding performance due to much rounding error generated by cascading lifting structures, our proposals can be applied to any PUFB without losing many ones because building blocks can be applied to every lifting block as it is. It is constructed with very simple structures and many rounding operations are eliminated. Additionally, the number of rounding operations is reduced more by using two-dimensional block transform (2DBT) of separated transform to each building block. As result, even though the proposed PUFBs require a little side information block (SIB), they show better coding performance in lossless-to-lossy image coding than the conventional ones.

This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.

Method for eliminating magnetic saturation in low-voltage and high-current DC-DC converter with fast dynamic response is described. The magnetic saturation is observed in onboard isolated bridge-type DC-DC converter due to inherently asymmetrical PWM signal during transient condition. The saturation is not eliminated by using ac-coupling capacitor for transformer. Mechanism of the saturation is analyzed and confirmed by experiments. Based on the analysis a solution for the magnetic saturation is proposed. The effectiveness of proposed method is also confirmed by experiments.

We proposed a new motion vector (MV) smoothing using fuzzy weighting and vector median filtering for frame rate up-conversion. A fuzzy reasoning system adjusts the weighting values based on the local characteristics of MV field including block difference and block boundary distortion. The fuzzy weighting removes the affect of outliers and irregular MVs from the MV smoothing process. The simulation results show that the proposed algorithm can efficiently correct wrong MVs and thus improve visual quality of the interpolated frames better than conventional methods.

A scheme for designing a hierarchical fuzzy classification system with a different number of fuzzy partitions based on statistical characteristics of the data is proposed. To minimize the number of misclassified patterns in intermediate layers, a method of fuzzy partitioning from the defuzzified outputs of previous layers is also presented. The effectiveness of the proposed scheme is demonstrated by comparing the results from five datasets in the UCI Machine Learning Repository.

Due to the detachability of Flash storage, which is a dominant portable storage, data integrity stored in Flash storages becomes an important issue. This study considers the performance of Flash Translation Layer (FTL) schemes embedded in Flash storages in conjunction with file system behavior that pursue high data integrity. To assure extreme data integrity, file systems synchronously write all file data to storage accompanying hot write references. In this study, we concentrate on the effect of hot write references on Flash storage, and we consider the effect of absorbing the hot write references via nonvolatile write cache on the performance of the FTL schemes in Flash storage. In so doing, we quantify the performance of typical FTL schemes for a realistic digital camera workload that contains hot write references through experiments on a real system environment. Results show that for the workload with hot write references FTL performance does not conform with previously reported studies. We also conclude that the impact of the underlying FTL schemes on the performance of Flash storage is dramatically reduced by absorbing the hot write references via nonvolatile write cache.

This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.

DTDs are continuously updated according to changes in the real world. Let t be an XML document valid against a DTD D, and suppose that D is updated by an update script s. In general, we cannot uniquely "infer" a transformation of t from s, i.e., we cannot uniquely determine the elements in t that should be deleted and/or the positions in t that new elements should be inserted into. In this paper, we consider inferring K optimum transformations of t from s so that a user finds the most desirable transformation more easily. We first show that the problem of inferring K optimum transformations of an XML document from an update script is NP-hard even if K = 1. Then, assuming that an update script is of length one, we show an algorithm for solving the problem, which runs in time polynomial of |D|, |t|, and K.

This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.

In this letter, we present a real-time orientation estimation and motion tracking scheme using interacting multiple model (IMM) based Kalman filtering method. Two nonlinear filters, quaternion-based extended Kalman filter (QBEKF) and gyroscope-based extended Kalman filter (GBEKF) are utilized in the proposed IMM-based orientation estimator for sensor motion state estimation. In the QBEKF, measurements from gyroscope, accelerometer and magnetometer are processed; while in the GBEKF, sole measurements from gyroscope are processed. The interacting multiple model algorithm is used for fusing the estimated states via adaptive model weighting. Simulation results validate the proposed design concept, and the scheme is capable of reducing overall estimation errors in sensor motion tracking.

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.

This paper presents a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower supply voltage. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects. Also, a new data-dependent adaptive time-domain pre-emphasis technique is proposed to compensate for the data-dependent jitter.