A new quadruple watermarking scheme of digital images against geometrical attacks is proposed in this letter. We treat the center and the four vertexes of the original image as the reference points and embed the same quadruple watermarks by means of polar coordinates, which is geometrically invariant. The center of an image is assumed to not to be removed after rotating, scaling and local distortions according to the general practical image processing. In the watermark extraction process, the vertexes of the image are found by a searching method. Thus watermark synchronization is obtained. Experimental results show that the scheme is robust to the geometrical distortions including rotation, scaling, cropping and local distortions.

A fast fc automatic tuning circuit suitable for WCDMA systems is proposed. The circuit employs master-slave architecture using digitally controlled Gm-C filter for avoiding long transient response. The tuning feedback loop contains a 2-bit up-down counter ADC for fast tuning operation. Furthermore, to avoid degradation of fc tuning accuracy due to reference feedthrough, an analog loop filter with notch located near reference frequency is used. The fast fc automatic tuning circuit is fabricated in a SiGe BiCMOS process. The tuning time within 200 µs is achieved for 35 chips from 2 lots and the standard deviation of 25.5 kHz is obtained for the average fc of 2.12 MHz.

Over the past ten years, the demand for low-cost, low-power, and small form-factor portable wireless devices has led to the integration of RF transceivers on the same silicon as digital processors to form wireless systems-on-a-chip. This paper describes the challenges in designing CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifiers, power amplifiers, mixers, and frequency synthesizers. System-on-a-chip integration issues such as leakage currents of digital logic, calibration techniques, and noise coupling are also discussed.

We propose a digital carrier recovery loop employing both a frequency detector and a phase detector for M-ary phase shift keying (MPSK) systems. A new frequency error correction function is also derived to increase the acquisition range. It is shown through computer simulation that the proposed scheme can reduce the acquisition time at large frequency offsets, unlike the existing ones.

In this paper, a novel independent component analysis (ICA) approach is proposed, which is robust against the interference of impulse noise. To implement ICA in a noisy environment is a difficult problem, in which traditional ICA may lead to poor results. We propose a method that consists of noise detection and image signal recovery. The proposed approach includes two procedures. In the first procedure, we introduce a self-organizing map (SOM) network to determine if the observed image pixels are corrupted by noise. We will mark each pixel to distinguish normal and corrupted ones. In the second procedure, we use one of two traditional ICA algorithms (fixed-point algorithm and Gaussian moments-based fixed-point algorithm) to separate the images. The fixed-point algorithm is proposed for general ICA model in which there is no noise interference. The Gaussian moments-based fixed-point algorithm is robust to noise interference. Therefore, according to the mark of image pixel, we choose the fixed-point or the Gaussian moments-based fixed-point algorithm to update the separation matrix. The proposed approach has the capacity not only to recover the mixed images, but also to reduce noise from observed images. The simulation results and analysis show that the proposed approach is suitable for practical unsupervised separation problem.

Since Smart Antenna technology has powerful spatial processing ability; it is regarded as a promising approach to enhancing the data rates and capacity of wireless LAN systems. In this paper, a small size, practical switched-beam antenna system, well suited for domestic in-home networking in the 2.4 GHz band, is designed and tested. The system has the configuration of regular nine-prism, and nine 1/4 wavelength rectangular patches are symmetrically distributed on the nine sides of the prism. The switching process is based on control of the microstrip used to feed the patch radiators, by placing PIN diodes at the microstrip feeding lines. The antenna array can generate nine beams with a gain of 11 dB. All the beams generated by the system are cophasal excited and have a 40°beamwidth. Compared to the uniform array, the system can guarantee the consistency of every beam and is preferable in shape.

In real-time systems, deadline misses of the tasks cause a degradation in the quality of their results. To improve the quality, we have to allocate CPU utilization for each task adaptively. Recently, Buttazzo et al. address a feedback scheduling algorithm, which dynamically adjusts task periods based on the current workloads by applying a linear elastic task model. In their model, the utilization allocated to each task is treated as the length of a linear spring and its flexibility is described by a constant elastic coefficient. In this paper, we first consider a nonlinear elastic task model, where the elastic coefficient depends on the utilization allocated to the task. We propose a simple iterative method for calculating the desired allocated resource and derive a sufficient condition for the convergence of the method. Next, we apply the nonlinear elastic model to an adaptive fair sharing controller. Finally, we show the effectiveness of the proposed method by computer simulation.

This paper studies nonlinear dynamics of a simplified model of multiple-input parallel buck converters. The dynamic winner-take-all switching is used to achieve N-phase synchronization automatically, however, as parameters vary, the synchronization bifurcates to a variety of periodic/chaotic phenomena. In order to analyze system dynamics we adopt a simple piecewise constant modeling, extract essential parameters in a dimensionless circuit equation and derive a hybrid return map. We then investigate typical bifurcation phenomena relating to N-phase synchronization, hyperchaos, complicated superstable behavior and so on. Ripple characteristics are also investigated.

The realization of k-nearest-matches search capability in fully-parallel mixed digital-analog associative memories by a sequential autonomous search mode is reported. The proposed concept and circuit implementation can be applied with all types of distance measures such as Hamming, Manhattan or Euclidean distance search, and the k value can be freely selected during operation. A test chip for concept verification has been designed in 0.35 µm CMOS technology with two-poly, three-metal layers, realizes k-nearest-matches Euclidean distance search and consumes 5.12 mm2 of the chip area for 64 reference patterns each with 16 units of 5-bit.

An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-µm CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm2 and 1.6 W, respectively.

For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.

In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor (SC) circuits, especially multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters. Theory and simulation results reveal that the settling time of MDACs can be decreased by optimizing the switch resistances. This switch resistance optimization does not only effectively increase the speed of single-bit MDACs, but also of multi-bit MDACs. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. With such an optimization, the response of the switch will be improved by up to 50%.

We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the ΔΣ modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two nine-level quantizers and four DACs are used in the modulator for low-power implementations and higher signal-to-noise-and-distortion (SNDR), but the nonlinearities of DACs are not noise-shaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18 µm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2. These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to low-IF receivers in wireless communication systems.

An integrated multi-level simulation environment is developed for a highly collision-resistant RFID system. An analog/mixed-signal (AMS) simulator for a circuit-level description of analog front-end power/signal transmission through electro-magnetic coupling is concurrently connected to a tailored software simulator for system-level description of digital back-end processing of TH-CDMA based anti-collision communication. The feasibility of the RFID system in which more than 1,000 transponders can be identified by a single reader in 400 msec is successfuly explored, under a practical presence of field disturbances such as background noises in communication channels as well as variations of electro-magnetic coupling strengths for power transmission.

Convolutional spreading CDMA with cyclic prefix (CS-CDMA/CP) is a multiuser interference-free (MUI-free) CDMA scheme proposed for multipath channels based on the convolution between user data and zero correlation zone (ZCZ) code, and its characteristics depend on the employed ZCZ codes. Although ternary ZCZ codes have more sequences than binary ZCZ codes in general, transmitted signal with ternary ZCZ codes give a slightly higher peak-to-average power ratio (PAPR). In this paper we propose the use of periodic ZCZ codes generated from an M-sequence which not only provides the same user capacity as ternary ZCZ codes but allows more design flexibility. Simulation results show that the new ZCZ code shows stronger robustness against an imperfect transmitter with clipping and enjoys better BER performances when used in CS-CDMA/CP compared to the conventional DS-CDMA with MRC-RAKE.

Traffic markers differentiate among packets from senders based on their service profile in the differentiated service networks. Researchers have previously revealed that the existing marking mechanism causes the unfairness in aggregates. This study presents a new marking algorithm. Simulation results demonstrate that the fairness of the proposed scheme exceeds that of SRTCM, TRTCM, TSWTCM and ITSWTCM for medium to high network provision levels.

In this paper, we introduce a syntactically embedded (s-embedded) language, and consider its principal congruence. The following three results are proved, where PL is the principal congruence of a language L, and W(L) is the residual of L. (1) For a language K, s-embedded in M, K is equal to a PM class. (2) For a language K, s-embedded in an infix language M, K is equal to a PW(M) class. (3) For a nonempty s-embedded language L, if L is double-unitary, then L is equal to a PW(M) class. From the above results, we can obtain those for principal congruence of some codes. For example, Ln is equal to a PLn+1 class for an inter code L of index n.

In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. First, it considers Look-Up Table (LUT) cascade realizations. Then, it introduces a new design technique called arithmetic decomposition by using LUTs and adders. Finally, it compares the amount of hardware and performance of radix converters implemented by FPGAs. 12-digit ternary to binary converters on Cyclone II FPGAs designed by the proposed method are faster than ones by conventional methods.

We measured the complex permittivities of whole blood and blood plasma in quasi millimeter and millimeter wave bands using a coaxial probe method. The validity of these measurements was confirmed by comparing with those of a different measurement method, i.e., a dielectric tube method. It is shown that the complex permittivities of the blood samples are similar to those of water in quasi millimeter and millimeter wave bands. Furthermore, the temperature dependences of the complex permittivities of the samples were measured.

A proactive cluster-based distance vector routing protocol based on DSDV protocol is proposed for mobile ad hoc networks. A network is divided into a number of clusters, each cluster having a clusterhead that directly connects the other nodes in the same cluster. Each clusterhead broadcasts update request (UREQ) messages at reqular intervals or in an event driven manner to its neighbor clusterheads. In this way, clusterheads update their own global routing tables that give a path among all clusterheads. In this process, multiple local paths from source clusterhead to its neighbor clusterheads are established as well. A node having a packet to send forwards the packet to its own clusterhead. The clusterhead determines next clusterhead with respect to the destination clusterhead by looking up its own global routing table. Then, the packet is delivered to the next clusterhead along a local path. The advantages of this protocol are threefold. The size of a global routing table is small since it has entries only for clusterheads. A UREQ message travels up from the initiating clusterhead to neighbor clusterheads. Hence, the convergence range of a update request is at least nine times as wide as that of DSDV or CGSR, increasing the correctness of routing. Lastly, a technique to bypass clusterheads, whenever possible, on the fly during packet transmission is presented, to reduce route length as well as to prevent clusterheads from becoming congested. Simulation results show that PCDV outperforms some key protocols of the same category greatly.