A new software based in-situ training (SBIST) method to achieve high accuracies is proposed for binarized neural networks inference accelerator chips in which measured offsets in sense amplifiers (activation binarizers) are transformed into biases in the training software. To expedite this individual training, the initial values for the weights are taken from results of a common forming training process which is conducted in advance by using the offset fluctuation distribution averaged over the fabrication line. SPICE simulation inference results for the accelerator predict that the accuracy recovers to higher than 90% even when the amplifier offset is as large as 40mV only after a few epochs of the individual training.

We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (Jc) of Josephson junctions (JJs) with respect to the design values, while the critical current (Ic) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm2 and the defect density is on the order of one defect for every 100,000 JJs.

In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.

The purpose of our research is to reproduce the appearance of frangible historical ink paintings for preserving frangible historical documents and illustrations. We, then, propose a method to reproduce both reflectance and transmittance of ink paintings simultaneously by stacking multiple sheets of printed paper. First, we acquire the relationship between printed ink patterns and the optical properties. Then, stacking printed multiple papers with acquired ink pattern according to the measurement, we realize to fabricate a photo-realistic duplication.

We evaluated a technique for protecting the copyright of digital data for 3-D printing. To embed copyright information, the inside of a 3-D printed object is constructed from fine domains that have different physical characteristics from those of the object's main body surrounding them, and to read out the embedded information, these fine domains inside the objects are detected using nondestructive inspections such as X-ray photography or thermography. In the evaluation, copyright information embedded inside the 3-D printed object was expressed using the depth of fine cavities inside the object, and X-ray photography were used for reading them out from the object. The test sample was a cuboid 46mm wide, 42mm long, and 20mm deep. The cavities were 2mm wide and 2mm long. The difference in the depths of the cavities appeared as a difference in the luminance in the X-ray photographs, and 21 levels of depth could be detected on the basis of the difference in luminance. These results indicate that under the conditions of the experiment, each cavity expressed 4 to 5bits of information with its depth. We demonstrated that the proposed technique had the possibility of embedding a sufficient volume of information for expressing copyright information by using the depths of cavities.

Key fabrication technology for the Pt/TiO2-x/TiO2/TiO2+x/Pt nano-film memristor is investigated, including preparing platinum (Pt) electrodes and TiO2-x/TiO2/TiO2+x nano-films. The effect of oxygen flow rate and deposition rate during fabrication on O:Ti ratio of thin films is demonstrated. The fabricated nano-films with different oxygen concentration are validated by the analyzed results from X-ray photoelectron spectroscopy (XPS). The obtained memristor device shows the typical resistive switching behavior and nonvolatile memory effects. An analytical device model for Pt/TiO2-x/TiO2/TiO2+x/Pt nano-film memristor is developed based on the fundamental linear relationships between drift-diffusion velocity and the electric field, and boundary conditions are also incorporated in this model. This model is able to predict the relation between variables in the form of explicit formula, which is very critical in memristor-based circuit designs. The measurement results from real devices validate the proposed analytical device model. Some deviations of the model from the measured data are also analyzed and discussed.

Industrial applications such as automotive ones require a cheap communication mechanism to send out communication messages from node to node by their deadline time. This paper presents a design paradigm in which we optimize both assignment of a network node to a bus and slot multiplexing of a FlexRay network system under hard real-time constraints so that we can minimize the cost of wire harness for the FlexRay network system. We present a cost minimization problem as a non-linear model. We developed a network synthesis tool which was based on simulated annealing. Our experimental results show that our design paradigm achieved a 50.0% less cost than a previously proposed approach for a virtual cost model.

Integrated InP polarization converters based on half-ridge structure are studied numerically. We demonstrate that the fabrication tolerance of the half-ridge structure can be extended significantly by introducing a slope at the ridge side and optimizing the thickness of the residual InGaAsP layer. High polarization conversion over 90% is achieved with the broad range of the waveguide width from 705 to 915~nm, corresponding to a factor-of-two or larger improvement in the fabrication tolerance compared with that of the conventional polarization converters. Finally we present a simple fabrication procedure of this newly proposed structure, where the thickness of the residual InGaAsP layer is controlled precisely by using a thin etch-stop layer.

We describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.

Monolithic integration of various kinds of optical components on a silicon wafer is the key to making silicon (Si) photonics practical technology. Applying silicon photonics to telecommunications further requires low insertion loss and polarization independence. We propose an integration concept for telecommunications based on Si and related materials and demonstrate monolithic integration of passive and dynamic functional components. This article shows the great potential of Si photonics technology for telecommunications.

This paper describes a new technique for the design of 3-terminal regulators in which the output voltage level can be adjusted without additional terminals or extra off-chip components. This circuit restricts the increase in the number of terminal pins by using a pin as both a voltage supply output and a voltage setup input. The voltage setup information is introduced using a serial control signal from outside the chip. Using the intermediate voltage level between the supply voltage and the regulator output, the adjustment data in the internal nonvolatile memory are safely updated without noise disturbance. To input the setup information into the chip in a stable manner, we developed a new 1-wire serial interface which combines key pattern matching and burst signal detection. To ensure high reliability, we suggested a quantitative method for evaluating the influence of noise in our new interface using a simple model with superimposed random noise. Circuits additional to those for a conventional 3-terminal regulator, include a 1-wire serial communication circuit, a low-capacity non-volatile memory, and a digital to analog (D/A) converter. A test chip was developed using 0.35 µm standard CMOS process, and there was almost no overhead to the conventional 3-terminal regulator in both chip area and power dissipation. In an on-board test with the test chip, we confirmed successful output voltage adjustment from 1.0 V to 2.7 V with approximately 6.5 mV precision.

We present a technology based on Nb/NbxSi1-x/Nb junctions, with barriers near the metal-insulator transition, for applications in superconducting electronics (SCE) as an alternative to Nb/AlOx/Nb tunnel junctions. Josephson junctions with co-sputtered amorphous Nb-Si barriers can be made with a wide variety of electrical properties: critical current density (Jc), capacitance (C), and normal resistance (Rn) can be reliably selected within wide ranges by choosing both the barrier thickness and Nb concentration. Nonhysteretic Nb/NbxSi1-x/Nb junctions with IcRn products greater than 1 mV, where Ic is the critical current, and Jc values near 100 kA/cm2 have been fabricated and are promising for superconductive digital electronics. These barriers have thicknesses of several nanometers; this improves fabrication reproducibility and junction uniformity, both of which are necessary for complex digital circuits. Recent improvements to our deposition system have allowed us to obtain better uniformity across the wafer.

The authors have demonstrated the local alignment of nematic liquid crystal with local micro-grating structure fabricated by the curing of an ultraviolet curable material via a three dimensional micro-fabrication technique known as two photon excitation direct laser writing [1]. The molecular alignment of the nematic liquid crystals on the fabricated micro-grating structures was firstly investigated by the observations of a local twisted nematic region in a liquid crystal cell made of a substrate with locally fabricated micro-grating structure and a counter substrate with rubbed polyimide. The optical polarizing microscope observation of the micro-grating structures indicated that liquid crystals molecules have aligned parallel to the grooves of the micro-grating structure and that local alignment was successfully achieved. The alignment characteristics of the liquid crystals on these micro-gratings was also investigated and discussed quantitatively in details through the measurement of anchoring energy by the conventional torque balance method and the Berreman method. The azimuthal anchoring energy for the micro-grating was found to be in the order of 10-6 J/m2 and inversely proportional to the grating period.

The unique properties of superconductivity can be exploited to provide the ultimate in electronic technology for systems such as ultra-precise analogue-to-digital and digital-to-analogue converters, precise DC and AC voltage standards, ultra high speed logic circuits and systems (both digital and hybrid analogue-digital systems), and very high throughput network routers and supercomputers which would have superior electrical performance at lower overall electrical power consumption compared to systems with comparable performance which are fabricated using conventional room temperature technologies. This potential for high performance electronics with reduced power consumption would have a positive impact on slowing the increase in the demand for electrical utility power by the information technology community on the overall electrical power grid. However, before this technology can be successfully brought to the commercial market place, there must be an aggressive investment of resources and funding to develop the required infrastructure needed to yield these high performance superconductor systems, which will be reliable and available at low cost. The author proposes that it will require a concerted effort by the superconductor and cryogenic communities to bring this technology to the commercial market place or make it available for widespread use in scientific instrumentation.

We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 11 µm, a line width of 0.8 µm, a JJ critical current density of 10 kA/cm2, a 2.4 Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120 GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.

Lasers have been established as a unique nanoprocessing tool due to its intrinsic three-dimensional (3D) fabrication capability and the excellent compatibility to various functional materials. Here we report two methods that have been proved particularly promising for tailoring 3D photonic crystals (PhCs): pinpoint writing via two-photon photopolymerization and multibeam interferential patterning. In the two-photon fabrication, a finely quantified pixel writing scheme and a method of pre-compensation to the shrinkage induced by polymerization enable high-reproducibility and high-fidelity prototyping; well-defined diamond-lattice PhCs prove the arbitrary 3D processing capability of the two-photon technology. In the interference patterning method, we proposed and utilized a two-step exposure approach, which not only increases the number of achievable lattice types, but also expands the freedom in tuning lattice constant.

We have designed, fabricated and characterized efficient optical resonators and low-threshold lasers based on planar photonic crystal concept. Lasers with InGaAsP quantum well active material emitting at 1550 nm were optically pumped, and room temperature lasing was observed at threshold powers below 220 µW. Porous high quality factor cavity that we have developed confines light in the air region and therefore our lasers are ideally suited for investigation of interaction between light and matter on a nanoscale level. We have demonstrated the operation of photonic crystal lasers in different ambient organic solutions, and we have showed that planar photonic crystal lasers can be used to perform spectroscopic tests on femtoliter volumes of analyte.

It is shown that the glass structure change is a simple and widely applicable method to modify refractive index locally in various glass fibers. A small part of a glass fiber is heated immediately to above its melt temperature by arc discharge, and then the molten fiber undergoes rapid cooling, which freezes the change of the glass structure. Therefore the refractive index of the fiber is decreased partially by the glass structure change induced by rapid solidification. The index reduction in a fiber fabricated from multicomponent glasses is estimated to be more than 0.006. To clarify that rapid solidification works for various glasses including silica glasses, long-period gratings are written in a standard telecommunication fiber with various discharge currents and times. The peak loss of more than 25 dB is obtained within only 6 periods. The index change can be adjusted by the discharge conditions. The gratings are not degraded by heating the whole gratings at 700C for 2 hours, and are highly temperature-stable. It is shown that resonance wavelengths can be tuned by controlling the heating temperature and heating time.

In-situ position-controlled lateral deposition of nanometer-size Zn and Al dots on a sapphire substrate was accomplished by dissociating diethylzinc and trimethylaluminum using an optical near field on a sharpened optical fiber probe tip. The minimum diameters of the Zn and Al dots deposited were 37 and 25 nm, respectively, comparable with the apex diameter of the fiber probe. By changing the reactant molecules during deposition, nanometric Zn and Al dots were successively deposited on the same sapphire substrate with high precision. The distance between these dots was as short as 100 nm.