The non-linear quasiparticle tunnel current flowing in a distributed superconductor-insulator-superconductor (SIS) transmission line resonator has been exploited in a low-noise heterodyne fixed-tuned waveguide receiver in the 600-700 GHz band. The mixer employs two half-wave or full-wave distributed SIS long junctions connected in series. These devices have been fabricated with optical lithography. At 654 GHz, a Y-factor of 1.79 has been recorded, corresponding to a double-side-band (DSB) receiver noise temperature of 198 K at an IF of 3 GHz.

This article addresses the problem of designing and implementing multigigabit post-detection filters for application in optical communication systems using optical soliton pulses. The designed filters have the main advantages of full integration, electrically adjustable frequency response and active input and output impedance match.

It is well known that interpath interference (IPI) is a major factor that limits the performance of high data rate transmissions over a variable spreading factor wideband-CDMA (W-CDMA) link since the spreading factor is in general small. An optimum combining scheme suppressing IPI was recently proposed for RAKE reception in [1]. The main contribution of this letter is to present a theoretical model for the outage probability and bit error probability of a RAKE receiver utilizing the optimum combining scheme. Analytical and simulation results are closely matched and show that the optimum scheme provides significant performance improvement compared to the conventional maximum ratio combining (MRC) scheme.

This paper proposes a new coherent CDMA channel structure for the uplink with staggered burst pilot and its detection algorithm. In the uplink, mobiles in a cell share a pilot channel by transmitting periodic bursts in nonoverlapping time slots, which enables coherent detection. We analyze the uplink capacity and derive the capacity formula. The dual mode channel estimator (DMCE) consists of pilot-based channel estimation (PBCE) and data-based channel estimation (DBCE). The proposed DMCE algorithm is very stable in the presence of Gaussian noise and Doppler shift because the pilot burst initiates the DMCE operation periodically. A negligible loss (0.068 dB) in Eb/N0 results from the introduction of the burst pilot. When compared with ideal (0 km/h) coherent detection, the required Eb/N0 in Doppler shift, corresponding to the speed of 160 km/h, is degraded less than 2.0 dB. The simulation result also shows increased channel capacity. The burst pilot can be implemented without added complexity even though some extra correlators are needed for the DMCE. This improvement is significant compared to previously published studies of coherent CDMA detectors with non-shared pilots.

We have developed a new planar lightwave circuit (PLC) platform eliminating Si terraces for hybrid integrated optical modules. This PLC platform has the advantage of a lower fabrication cost than the conventional PLC platform with an Si terrace, because it does not require fabrication processes such as Si terrace forming and mechanical polishing. Using our new PLC platform structure, we fabricated a transceiver for optical access networks and an 8-channel multi-channel photoreceiver for wavelength division multiplexing (WDM) interconnection systems.

We have developed a new planar lightwave circuit (PLC) platform eliminating Si terraces for hybrid integrated optical modules. This PLC platform has the advantage of a lower fabrication cost than the conventional PLC platform with an Si terrace, because it does not require fabrication processes such as Si terrace forming and mechanical polishing. Using our new PLC platform structure, we fabricated a transceiver for optical access networks and an 8-channel multi-channel photoreceiver for wavelength division multiplexing (WDM) interconnection systems.

In quantum communication theory, a realization of the optimum quantum receiver that minimizes the error probability is one of fundamental problems. A quantum receiver is described by detection operators. Therefore, it is very important to derive the optimum detection operators for a realization of the optimum quantum receiver. In general, it is difficult to derive the optimum detection operators, except for some simple cases. In addition, even if we could derive the optimum detection operators, it is not trivial what device corresponds to the operators. In this paper, we show a realization method of a quantum receiver which is described by a projection-valued measure (PVM) and apply the method to 3-ary phase-shift-keyed (3PSK) coherent-state signals.

12-channel DC to 622-Mbit/s/ch optical transmitter and receiver have been developed for high-capacity and rather long (about 100 m) bit-parallel raw data transmission in intra- and inter-cabinet interconnection of large-scale switching, routing and computing system. Bit-parallel raw data transmission is done by using a bit-by-bit operational automatic decision threshold control receiver circuit with a DC-coupled configuration, the pin-PDs with their anodes and cathodes separated in a channel-by-channel manner, and a receiver preamplifier with a low-pass filter. The transmitter consists of a 12-channel LD sub-assembly unit and a LD driver LSI. The LD sub-assembly unit consists of a 12-channel array of high temperature characteristic 1.3-µm planar buried hetero-structure (PBH) LDs and 62.5/125 graded-index multi-mode fibers (GI62.5 MMFs). The 1.3-µm PBH LDs and the GI62.5 MMFs are optically coupled by passively visual alignment technology on the Si V-groove. The receiver consists of a 12-channel pin-PD sub-assembly unit and a receiver LSI. The pin-PD sub-assembly unit consist of a 12-channel array of pin-PDs and GI62.5 MMFs. They are optically coupled by using a flip-chip bonding on the Si V-groove. The transmitter and receiver each have eleven data channels and one clock channel. The size is as small as 3.6 cc for each modules, and the power consumptions are 1.7 W (transmitter) and 1.35 W (receiver). They transmitted a bit-parallel raw data through a 100-meter ribbon of GI62.5 MMFs in an ambient temperature range of 0-70C. They provide a synchronous PECL interface parallel link for with a 3.3-V single power supply.

A direct conversion receiver IC including an on-chip balun, an I/Q mixer, a variable gain amplifier and a 90 phase-shifter is fabricated in a Bi-CMOS technology with 15 GHz transition frequency (fT). This paper demonstrates that cascaded connection of an on-chip balun and a double balanced mixer as the I/Q mixer is effective to achieve a low DC offset and a low second-order distortion, on the basis of both careful examination of the mixer behavior and measurement. Input-referred DC offset voltage of less than 300 µV and spurious free dynamic range (SFDR) of over 67 dB are obtained by measurement. The IC consumes 52 mA from 2.7 V power supply voltage. The die size is 3 mm 3 mm.

We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.

In DS-CDMA (including W-CDMA), a received signal can be resolved into multiple paths to be Rake combined. An important design problem of the Rake receiver is how to accurately search the paths with a sufficiently large signal-to-interference plus background noise power ratio (SIR). This paper investigates the performance of a coherent Rake receiver using pilot symbol-assisted channel estimation with fast transmit power control, and thereby optimizes three key parameters: the total averaging period, Tavg, consisting of a combination of coherent summation and power summation; each period of the summations for measuring the average power delay profile; and path-selection threshold M from the generated power delay profile. We used a path search algorithm, which searches the paths that have M times greater average signal power than the interference plus background noise power measured in the average power delay profile generated using time-multiplexed pilot symbols. It was clarified by both simulation and laboratory experiments that when M = 4, Tavg = 50-100 msec, and the number of slots for coherent accumulation R = 2, the required average transmit Eb/N0 for obtaining the average BER of 10-3 is almost minimized with and without antenna diversity for both ITU-R Vehicular-B and average equal power L-path delay profile model, in which each path suffered independent Rayleigh fading. The paper also shows that based on the field experiments, the path search algorithm with optimized path-selection parameters is robust against actual dynamic changes in the power delay profile shape.

A rack-mounted prototype packet switch that makes use of wavelength-division-multiplexing (WDM) interconnect techniques has been developed. The switch has a maximum throughput of 320 Gbit/s. It features a WDM star-based switch architecture, an electrical control circuit layer and a broad-bandwidth optical WDM layer. The basic characteristics of the broad bandwidth WDM layer, such as level diagram, transmission characteristics, 32-wavelength-channel switching, and high-speed optical gating within a 1.6-ns guard time, are described. Experimental results demonstrated that the switch can perform practical self-routing switch operations, such as address-extraction, optical buffering, and filtering for packet speeds of up to 10 Gbit/s. The switch is promising for such applications as a terabit-per-second switching node in future WDM transport networks.

In this letter, a new rapid converging method based on orthogonalization is proposed. Our approach is to find the near-optimum coefficient values during training period, and then use them as the initial values of the LMS algorithm. The numerical results show that the rapid convergence speed of the proposed scheme does not depend on the eigenvalue spread.

This paper proposes a new parallel high speed mobile radio transmission scheme using cyclic-shifted-codes generated from a modified M-sequence. The modified M-sequence is biased with constant direct current (dc) on an M-sequence and is inserted the guard chips before and after this biased M-sequence. The proposed system has the following features: i) Orthogonality of the codes is kept not only between direct waves of each parallel channels but also between direct and delayed waves within the guard chips; ii) It is possible to reduce the number of kinds of codes allocated to one user; and iii) It is easy to recover both code and chip timings. In this paper, moreover, the performance of the proposed system was evaluated in terms of bit error rate (BER) under additive white Gaussian noise (AWGN), non-selective one path Rayleigh fading and double-spike Rayleigh fading channels. As a result, the proposed transmission scheme can transmit several Mbps in a high-speed double-spike Rayleigh fading channel with better quality in comparison with a conventional multicode CDM transmission scheme based on M-sequences.

An ultra low-noise and highly selective, experimental 2-GHz band cryogenic receiver front end (CRFE) has been newly developed for cellular base stations. It utilizes a high-Q superconducting filter, a very low noise cryogenic amplifier, and a highly reliable cooler that is very compact. Fundamental design of the CRFE is investigated. First, the equivalent noise temperature of the CRFE and the effect of improving CRFE sensitivity on base station reception are discussed. Next, essential technologies and fundamental characteristics of each component are described. Finally, influence of antenna noise, such as ground noise and man-made noise, is estimated through field tests both in urban and suburban areas.

This paper analyses the performance of a joint receiving structure for DS-CDMA communications systems. To reduce undesirable performance degradation due to the multiple access interferences and the near-far problem in multipath fading channel environment, this paper exploits the receiving structure for the multiuser communication composed of a beamformer-RAKE receiver and a decorrelating multiuser detector. The proposed DS-CDMA receiving structure mitigates the performance impairment invoked from the noise enhancement and reveals less computational complexity by utilizing the multipath temporal combiner prior to accessing the decorrelating detection. Also an efficient block Toeplitz inversion technique using the matrix Levinson polynomials is introduced to further diminish the computational burden encountered from applying the decorrelating multiuser detection process as in usual. Simulation results are conducted to demonstrate the superior performance of the proposed multiuser detection structure in multipath fading CDMA channel.

It is expected that software receivers will be widely available for radio communication, broadcasting and radio monitoring applications because they are able to be equipped with multimode, multirate and multiband functions in a single hardware platform. This paper describes the basic techniques required for software receivers for both hardware and software. The evaluation items and methods were studied and some evaluations done with an experimental software receiver model fabricated for radio monitoring applications. Future concepts in radio communication, broadcasting and radio monitoring applications where software receivers are thought to be suitable, were studied, and problems for realization identified.

10-Gbit/s monolithic receiver OEIC's for 1.55-µm optical transmission systems were fabricated using a stacked layer structure of p-i-n photodiodes and HEMT's grown on InP substrates by single-step MOVPE. A receiver OEIC with a large O/E conversion factor was obtained by adding a three-stage differential amplifier to a conventional feedback amplifier monolithically integrated with a surface-illuminated p-i-n photodiode. The circuit configuration gave a preamplifier a transimpedance of 60 dBΩ. The receiver OEIC achieved error-free operation at 10 Gbit/s without a postamplifier even with the optical input as low as -10.3 dBm because of its large O/E conversion factor of 890 V/W. A two-channel receiver OEIC array for use in a 10-Gbit/s parallel photoreceiver module based on a PLC platform was made by monolithically integrating multimode WGPD's with HEMT preamplifiers. The side-illuminated structure of the WGPD is suitable for integration with other waveguide-type optical devices. The receiver OEIC arrays were fabricated on a 2-inch wafer with achieving excellent uniformity and a yield over 90%: average transimpedance and average 3-dB-down bandwidth were 43.8 dBΩ and 8.0 GHz. The two channels in the receiver OEIC array also showed sensitivities of -16.1 dBm and -15.3 dBm at 10 Gbit/s. The two-channel photoreceiver module was constructed by assembling the OEIC array on a PLC platform. The frequency response of the module was almost the same as that of the OEIC chip and the crosstalk between channels in the module was better than -27 dB in the frequency range below 6 GHz. These results demonstrate the feasibility of using our receiver OEIC's in various types of optical receiver systems.

This paper reviews the operation, design, and performance of the uni-traveling-carrier-photodiode (UTC-PD). The UTC-PD is a new type of photodiode that uses only electrons as its active carriers and its prime feature is high current operation. A small signal analysis predicts that a UTC-PD can respond to an optical signal as fast as or faster than a pin-PD. A comparison of measured pulse photoresponse data reveals how the saturation mechanisms of the UTC-PD and pin-PD differ. Applications of InP/InGaAs UTC-PDs as optoelectronic drivers are also presented.

This paper presents the bit-error rate (BER) performance of the RAKE receiver over a multipath Rayleigh fading channel. The closed-form BER in the downlink single-cell environment is obtained through the analysis of the imperfect channel estimation. We compute the BER as a function of energy-to-noise ratio per bit including the effect of multiple access interference and multipath interference, with channel and system parameters: number of diversity channels L = 1, 3, 6, 12; Doppler frequency shift with fD T = 0.008333, 0.0167, 0.025; residual carrier frequency offset Δ f = -600 600 Hz; averaging length of the channel estimator Np = 128-1536 chips. This analysis allows predicting the system's performance and helps to optimize the parameter setting for the channel estimation process. We show that even if the optimal system parameters are used, the BER performance results in a minimal 4dB degradation in comparison to the perfect channel estimation. Finally, the theoretical results are verified by using the Monte-Carlo computer simulations.