A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.

A high-speed and low-power 8-bit subranging analog-to-digital converter (ADC) based on 65-nm CMOS technology was fabricated. Rather than using digital foreground calibration, an analog-centric approach was adopted to reduce power dissipation. An offset cancelling charge-steering amplifier and capacitive-averaging technique effectively reduce the offset, noise, and power dissipation of the ADC. Moreover, the circuit used to compensate the kickback noise current from the comparator can also reduce the power dissipation. The reference-voltage generator for the fine ADC is composed of a fine ladder and a capacitor providing an AC signal path. This configuration reduces the power dissipation of the selection signal drivers for the analog multiplexer. A test chip fabricated using 65-nm digital CMOS technology achieved a high sampling rate of 1GHz, a low power dissipation of 17.5mW, and a figure of merit of 118fJ/conv.-step.

Superconducting integrated circuits should be operated at low temperature below a half of their critical temperatures. Thermal heat from a bias resistor could rise the temperature in Josephson junctions, and would reduce their critical currents. In this study, we estimate the temperature in a Josephson junction heated by a bias resistor at the bath temperature of 4.2 K, and introduce a parameter β that connects the thermal heat from a bias resistor and the temperature elevation of a Josephson junction. By using β, the temperature in the Josephson junction can be estimated as functions of the current through the resistor.

A matched load for post-wall waveguide (SIW; Substrate Integrated Waveguide) is presented. It consists of an electrically-shorted post-wall waveguide and a rectangular thin-film resistor sheet on the surface of the waveguide, resulting in a quite compact structure without three-dimensional bulky absorber as in conventional waveguide matched loads. A fabricated X-band matched load has achieved less than -20 dB reflection in more than 20% relative bandwidth.

In this paper, a 24 GHz frequency source for low phase noise is presented in a 0.18 µm CMOS process. The 24 GHz frequency source chip is composed of a 12 GHz voltage controlled oscillator (VCO) and a 24 GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12 GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17 dBc/Hz at a 1 MHz offset frequency and -20.95 dB at 23.19 GHz frequency, respectively. The measured frequency tuning range is from 23.19 GHz to 24.76 GHz drawing 2.72 mA at a supply voltage of 1.8 V not including an output buffer.

This paper presents a resistor-compensation technique for a CMOS bandgap and current reference, which utilizes various high positive temperature coefficient (TC) resistors, a two-stage operational transconductance amplifier (OTA) and a simplified start-up circuit in the 0.35-µm CMOS process. In the proposed bandgap and current reference, numerous compensated resistors, which have a high positive temperature coefficient (TC), are added to the parasitic n-p-n and p-n-p bipolar junction transistor devices, to generate a temperature-independent voltage reference and current reference. The measurements verify a current reference of 735.6 nA, the voltage reference of 888.1 mV, and the power consumption of 91.28 µW at a supply voltage of 3.3 V. The voltage TC is 49 ppm/ in the temperature range from 0 to 100 and 12.8 ppm/ from 30 to 100. The current TC is 119.2 ppm/ at temperatures of 0 to 100. Measurement results also demonstrate a stable voltage reference at high temperature (> 30), and a constant current reference at low temperature (< 70).

We propose a CMOS circuit that can be used as an equivalent to resistors. This circuit uses a simple differential pair with diode-connected MOSFETs and operates as a high-resistance resistor when driven in the subthreshold region of MOSFETs. Its resistance can be controlled in a range of 1-1000 MΩ by adjusting a tail current for the differential pair. The results of device fabrication with a 0.35-µm 2P-4M CMOS process technology is described. The resistance was 13 MΩ for a tail current of 10 nA and 135 MΩ for 1 nA. The chip area was 105 µm110 µm. Our resistor circuit is useful to construct many high-resistance resistors in a small chip area.

The sub-threshold R-MOSFET resistor structure which enables tuning range extension below the threshold voltage in the MOSFET with moderate to weak inversion operation is analyzed in detail. The principal operation of the sub-threshold resistor is briefly described. The analysis of its characteristic based on approximations of a general MOS equation valid for all regions is given along with discussion on design implication and consideration. Experiments and simulations are provided to validate the theoretical analysis and design, and to verify the feasibility at a supply voltage as low as 0.5 V using a low-threshold devices in a 1.8-V 0.18 µm CMOS process.

As the basic study of the electromagnetic interference (EMI) problem at the circuit elements, the near magnetic field distributions above resistors for the termination of a transmission line are measured to reveal the profile of radiation. Five kinds of resistors and two types of resistance values are sampled. The results showed that the variation of the near magnetic field distribution above the transmission line is effected largely by the reactance of the resistor at the high frequency. These results are the basis for the design of the structure of the component.

This letter presents the characteristics of complex antenna factors of a resistor loaded dipole antenna with a balun consisting of two coaxial feeders (coaxial cable balun). The resistor loading is used to realize dipole antennas with higher fidelity than unloaded dipole equivalents. The complex antenna factor for a resistor loaded dipole antenna with coaxial cable balun is derived by extending the power loss concepts. The numerical results show that the series resistor loaded dipole antenna offers higher fidelity than the unloaded dipole. The result of the calculated complex antenna factors are in good agreement with that of the measured results.

In this letter, my proposals for a Floating node voltage-controlled Variable Resistor circuit (FVR) are based upon its advantages as linear and compact. The performance of the proposed circuit was confirmed by PSpice simulation. The simulation results are reported in this letter.

A novel asymmetric tapered-line power divider is presented. It has several strip resistors which are formed like a ladder between the tapered-line conductors to achieve a good output isolation. The equivalent circuits are derived with the even/odd-mode analysis. These equivalent circuits are employed to design the asymmetric power divider. The fabricated asymmetric power divider with 1:2 power dividing ratio shows broadband performances in return loss and isolation which are greater than 19 dB over a 3:1 bandwidth in the C-Ku bands.

A new moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results have demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with on-chip terminated resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, furthermore, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 µm 2-poly 3-metal CMOS technology, and it occupies 1350 µm750 µm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.

An 8-GS/s 4-bit CMOS analog-to-digital converter (ADC) chip was implemented by using a time interleaved flash architecture for very high frequency mixed signal applications with a 0.18-µm single-poly five-metal CMOS process. Eight 1-GS/s flash ADCs were time-interleaved to achieve the 8-GHz sampling rate. Eight uniformly-spaced 1 GHz clocks were generated by using a phase-locked-loop (PLL) with the peak-to-peak and rms jitters of 29.6 ps and 3.78 ps respectively. An input buffer including a preamplifier array (fifteen preamplifiers, four dummy amplifiers and averaging resistors) was shared among eight 1-GS/s flash ADCs to reduce the input capacitance and the mismatches among eight 1-GS/s flash ADCs. The adjacent output nodes of preamplifiers were connected by a resistor (resistor-averaging) to reduce the effects of the input offset voltage and the load mismatches of preamplifiers. A source follower circuit was added at the output node of a preamplifier to drive eight distributed track and hold (DTH) circuits. The Input bandwidth of ADC was measured to be 2.5 GHz. The measured SFDR values at the sampling rate of 8-GS/s were 25 dB and 22 dB for the 1.033 GHz and 2.5 GHz sinusoidal input signals respectively. The power consumption and the active input voltage range were 340 mW and 700 mV peak-to-peak, respectively, at the sampling rate of 8-GS/s and the supply voltage of 1.8 V. The active chip area was 1.32 mm2.

In this letter, a linear variable resistor circuit using an FG-MOSFET (floating-gate MOSFET) is proposed. This is based on Schlarmann's variable resistor and is very simple. The advantage of the proposed circuit is a wide-input range. The utility of the proposed circuit was confirmed by HSPICE simulation with 1.2 µm CMOS process parameters. The simulation results are reported in this letter.

A constant voltage/constant current (CV/CC) parallel operation heterojunction bipolar transistor (HBT) power amplifier (PA) configuration is presented, and its design method is described. A resistor base feed (CC mode) HBT is connected to an inductor base feed (CV mode) HBT in parallel, and compensates the gain expansion of the CV mode HBT due to near class-B operation. By adding CC mode HBT, the total quiescent current can be decreased from 32 mA to 23 mA with adjacent channel leakage power ratio (ACPR) < -40.0 dBc. At the maximum output power region, the fabricated PA achieves output power (Pout) of 26.8 dBm and power added efficiency (PAE) of 42.0% with ACPR of -40.0 dBc, and shows the comparable performances with a conventional PA using CV mode HBT.

An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.

This paper describes a three-port power divider with compensation networks for non-ideal isolation resistor. The compensation networks consist of two pairs of transmission lines and cancel out the parasitic reactance of the non-ideal isolation resistor. The design equations to provide perfect return loss and isolation at a center frequency are presented. The availability of the proposed power divider has been verified by the comparison between calculated and experimental results in the Ku-band.

In this paper, we propose a floating resistor circuit with positive and negative resistance operating at the low supply voltages 1.5 V. Only two transistors are connected between supply lines in order to operate under the low power supply voltages. In this circuit, current subtraction is carried out at the gate terminal for which input/output voltage is applied. As a result, the proposed circuit can realize the large range of resistance of positive and negative resistances. Therefore, in an application, the proposed circuit is used in neuro-based limit cycle generator as synaptic weights.