We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.

We have developed the world's largest 16.7-inch hybrid in-cell touch panel. To realize the large sized in-cell touch panel, we applied a vertical Vcom system and low resistance sensor, which are JDI's original technologies. For glove touch function, we applied mutual bundled driving, which increases the signal intensity higher. The panel also has a low surface reflection, curved-shaped, and non-rectangular characteristics, which are particular requirements in the automotive market. The over 15-inch hybrid in-cell touch panel adheres to automotive quality requirements. We have also developed a force touch panel, which is a new human machine interface (HMI) based on a hybrid in-cell touch panel in automotive display. This study reports on the effect of the improvements on the in-plane variation of force touch and the value change of the force signal under different environment conditions. We also a introduce force touch implemented prototype.

A novel algorithm is proposed for estimating the direction of arrival (DOA) of linear frequency modulated (LFM) signals for the uniform circular array (UCA). Firstly, the UCA is transformed into an equivalent virtual uniform linear array (ULA) using the mode-space algorithm. Then, the short time Fourier transform (STFT) of each element's output is worked out. We can obtain the spatial time-frequency distribution matrix of the virtual ULA by selecting the single-source time-frequency (t-f) points in the t-f plane and then get the signal subspace of the array. The characteristics nature of the Bessel function allow us to obtain the multiple invariance (MI) of the virtual ULA. So the multiple rotational invariant equation of the array can be obtained and its closed-form solution can be worked out using the multi-least-squares (MLS) criterion. Finally, the two dimensional (2-D) DOA estimation of LFM signals for UCA can be obtained. Numerical simulation results illustrate that the UCA-STFT-MI-ESPRIT algorithm proposed in this paper can improve the estimation precision greatly compared with the traditional ESPRIT-like algorithms and has much lower computational complexity than the MUSIC-like algorithms.

Asymmetrically designed polycrystalline silicon (poly-Si) thin film transistors (TFT) were fabricated and investigated to suppress kink effect and to improve electrical reliability. Asymmetric dual channel length poly-Si TFT (ADCL) shows the best reduction of kink and leakage currents. Technology computer-aided design simulation proves that ADCL can induce properly high voltage at floating node of the TFT at high drain-source voltage (VDS), which can mitigate the impact ionization and the degradation of the transconductance of the TFT showing high reliability under the hot carrier stress.

Amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistor (TFT) was fabricated by an advanced self-aligned imprint lithography (ASAIL) method with a hybrid etching process. The SAIL is a top-down method to fabricate a TFT using a three-dimensional multilayer etch mask having all pattern information for the TFT. The hybrid etching process was newly applied in the original SAIL process for the purpose of reducing plasma damage of a-IGZO channel layer during plasma etching in the ASAIL process. This research demonstrated that the a-IGZO TFT could be successfully fabricated by the ASAIL process. In particular, the hybrid etching process applied in this paper can be utilized for the back-channel-etch type a-IGZO TFT and further extended for the roll-to-roll backplane process.

We report room-temperature atomic layer deposition (ALD) of SnO2 using tetramethyltin (TMT) as a precursor and plasma-excited humidified argon as an oxidizing gas and investigate the saturation behaviors of these gases on SnO2-covered Si prisms by IR absorption spectroscopy to determine optimal precursor/oxidizer injection conditions. TMT is demonstrated to adsorb on the SnO2 surface by reacting with surface OH groups, which are regenerated by oxidizing the TMT-saturated surface by plasma-excited humidified argon. We provide a detailed discussion of the growth mechanism. We also report the RT ALD application to the RT TFT fabrication.

This paper proposes a read-only memory driving circuit for RFID tags based on a-IGZO thin-film transistors. The circuit consists of a Johnson counter and monotype complementary gates. By utilizing complementary signals to drive a decoder based on monotype complementary gates, the propagation delay can be decreased and the redundant current can be reduced. The Johnson counter reduces the number of registers. The new circuit can effectively avoid glitch generation, and reduce circuit power consumption and delay.

Enhancing the performance of low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) requires high-quality poly-Si films. One of the authors (A.H.) has already demonstrated a continuous-wave (CW) laser lateral crystallization (CLC) method to improve the crystalline quality of thin poly-Si films, using a diode-pumped solid-state CW laser. Another candidate method to increase the on-current and decrease the subthreshold swing (s.s.) is the use of a high-k gate stack. In this paper, we discuss the performance of top-gate CLC LT poly-Si TFTs with sputtering metal/hafnium oxide (HfO2) gate stacks on nonalkaline glass substrates. A mobility of 180 cm2/Vs is obtained for n-ch TFTs, which is considerably higher than those of previously reported n-ch LT poly-Si TFTs with high-k gate stacks; it is, however, lower than the one obtained with a plasma enhanced chemical vapor deposited SiO2 gate stack. For p-ch TFTs, a mobility of 92 cm2/Vs and an s.s. of 98 mV/dec were obtained. This s.s. value is smaller than the ones of the previously reported p-ch LT poly-Si TFTs with high-k gate stacks. The evaluation of a fabricated complementary metal-oxide-semiconductor inverter showed a switching threshold voltage of 0.8 V and a gain of 38 at an input voltage of 2.0 V; moreover, full swing inverter operation was successfully confirmed at the low input voltage of 1.0 V. This shows the feasibility of CLC LT poly-Si TFTs with a sputtered HfO2 gate dielectric on nonalkaline glass substrates.

A negative capacitor is fabricated using poly(vinylidene fluoride-trifluoroethylene) copolymer and connected in series to an a-IZO TFT. It is experimentally demonstrated that the negative capacitance of the negative capacitor can create steep switching in the a-IZO TFT (e.g., a subthreshold slope change from 342mV/decade to 102mV/decade at room-temperature).

We have developed a capacitance sensor of frequency modulation for integrated touchpanels using amorphous In-Sn-Zn-O (α-ITZO) thin-film transistors (TFTs). This capacitance sensor consists of a ring oscillator, whose one stage is replaced by a reset transistor, sensing transistor, and sensing electrode. The sensing electrode is prepared as one terminal to form a sensing capacitor when the other terminal is added by a finger. The ring oscillator consists of pseudo CMOS inverters. We confirm that the oscillation frequency changes when the other terminal is added. This result suggests that this capacitance sensor can be applied to integrated touchpanels on flatpanel displays.

Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below $550^{circ}$C, to realize high performance and low power dissipation system-on-glass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substrate and the TG was fabricated by a self-alignment process using the BG as a photomask. This structure is called embedded metal double-gate (E-MeDG) in this paper. The poly-Si channel with lateral large grains was fabricated using a continuous-wave laser lateral crystallization (CLC). The self-aligned 4T E-MeDG LT poly-Si TFT, with a gate length of 5,$mu $m and TG and BG SiO$_2$ thicknesses of 50 and 100,nm, respectively, exhibited a subthreshold swing of 120,mV/dec and a threshold voltage ($mathrm{V}_{mathrm{th}}$) of $-$0.5,V in the connecting DG mode; i.e. when TG is connected to BG. In the TG operation at various BG control voltage, a threshold voltage modulation factor $(gamma = Delta mathrm{V}_{mathrm{th}}/Delta mathrm{V}_{mathrm{BG}})$ of 0.47 at negative BG control voltage and 0.60 at positive BG control voltage are demonstrated, which values are nearly equal to theoretical prediction of 0.40 and 0.75. Trend of subthreshold swing (s.s.) of TG operation under different BG control voltage are also consistent with theoretical prediction. In addition to TG operation, successful BG operation under various TG control voltages was confirmed. Field-effect mobility derived from g$_{mathrm{m}}$ also varied depending on control gate voltage. The high controllability of device parameter of individual LT poly-Si TFTs is caused by excellent crystalline quality of CLC poly-Si film and will enable us to the fabrication of high-speed and low power-dissipation SoG.

We propose a temperature sensor employing a ring oscillator composed of poly-Si thin-film transistors (TFTs). Particularly in this research, we compare temperature sensors using TFTs with lightly-doped drain structure (LDD TFTs) and TFTs with offset drain structure (offset TFTs). First, temperature dependences of transistor characteristics are compared between the LDD and offset TFTs. It is confirmed that the offset TFTs have larger temperature dependence of the on current. Next, temperature dependences of oscillation frequencies are compared between ring oscillators using the LDD and offset TFTs. It is clarified that the ring oscillator using the offset TFTs is suitable to detect the temperature. We think that this kind of temperature sensor is available as a digital device.

It is clarified that the SiN$_{mathrm{X}}$ film with a thickness of 1.7 nm, which was formed at the interface between the poly-Si source/drain and Al layer, suppresses the hump phenomenon of TFT with a channel length of 10, $mu $m. The mechanism of the hump suppression by this structure is discussed. It is thought that the fixed charge in the SiN$_{mathrm{X}}$ film suppresses the formation of the parasitic channel in the poly-Si edge by the Coulomb repulsion.

We applied a roll-to-sheet imprinting process to a large-scale substrate. Patterned ruthenium oxide (RuO$_{2}$) electrodes were fabricated on both glass and flexible substrates. The resistivity of the electrodes on a glass substrate was $3.5 imes 10^{-5} Omega $ cm, which indicates that this technique is useful for the fabrication of thin-film transistor (TFT) electrodes.

Excimer laser annealing at 308nm in UV and semiconductor blue laser-diode annealing at 445nm were performed and compared in term of the crystallization depending on electrical properties of Si films. As a result for the thin Si films of 50nm thickness, both lasers are very effective to enlarge the grain size and to activate electrically the dopant atoms in the CVD Si film. Smooth Si surface can be obtained using blue-laser annealing of scanned CW mode. By improving the film quality of amorphous Si deposited by sputtering for subsequent crystallization, both laser annealing techniques are effective for LTPS applications not only on conventional glass but also on flexible sheet. By conducting the latter advanced annealing technique, small grain size as well as large grains can be controlled. As blue laser is effective to crystallize even rather thicker Si films of 1µm, high performance thin-film photo-sensor or photo-voltaic applications are also expected.

A multigate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) is a recently popular topic in the field of Si devices. In this study, self-aligned planar metal double-gate poly-Si TFTs consisting of an embedded bottom metal gate, a top metal gate fabricated by a self-alignment process, and a lateral poly-Si film with a grain size greater than 2 µm were fabricated on a glass substrate at 550. The nominal field-effect mobility of an n-channel TFT is 530 cm2/Vs, and its subthreshold slope is 140 mV/dec. The performance of the proposed TFTs is superior to that of top-gate TFTs fabricated using equivalent processes.

A CMOS current-mode S-shape correction circuit with shape-adjustable control is proposed for suiting different LCD panel's characteristics from different manufactures. The correction shape is divided into three segments for easy curve-fitting using three lower order polynomials. Each segment could be realized by a corresponding current-mode circuit. The proposed circuit consists of several control points which are designed for tuning the correction shape. The S-shape correction circuit was fabricated using the 0.35 µm TSMC CMOS technology. The measured input dynamic range of the circuit is from 0 µA to 220 µA. The -3 dB bandwidth of the circuit is up to 262 MHz in a high input current region.

We have succeeded in developing high-performance p-type of organic semiconductors with phenylethynyl groups, which have high filed-effect mobilities (>3 cm2V-1s-1) by improving molecular planarity. A single crystal of the organic semiconductors has a herringbone structure. It plays an important role for carrier transport. In addition, we found that they had lower contact resistances to Au electrodes as well. Then, we used the materials for the carrier injection layer deposited onto another organic semiconductor we developed recently, which achieved a high field-effect mobility, and a low threshold voltage (Vth).

We report on the fabrication of coplanar dual-gate ZnO thin-film transistors with 200-nm thickness SiNx for both top and bottom dielectrics. The ZnO film was deposited by RF magnetron sputtering on SiO2/Si substrates at 100. And the thickness of ZnO film is compared with 100-nm and 40-nm. This TFT has a channel width of 100-µm and channel length of 5-µm. The fabricated coplanar dual-gate ZnO TFTs of 40-nm-thickness exhibits a field effect mobility of about 0.29 cm2/V s, a subthreshold swing 420 mV/decade, an on-off ratio 2.7107, and a threshold voltage 0.9 V, which are greatly improved characteristics, compared with conventional bottom-gate ZnO TFTs.

Motion blur in TFT-LCD is caused by sample and hold characteristic, slow response time of liquid crystal, and the inconsistency between object tracking of the human eye and the actual object location. In order to solve this problem, a high frame rate driving method based on motion estimation and motion compensation has been applied to LCD products. However, as the required processing time of motion estimation increases in LCD TV and monitor systems, real-time video image processing becomes more difficult. Frame interpolation through the large macro block (MB) size has limitations to detect small objects. So, this paper proposes the efficient motion estimator architecture which uses seven kinds of macro blocks to enhance the accuracy of motion estimation and combines the parallel processing with pre-computation technology and hardware optimization for high-speed processing. Also, for increased efficiency in the hardware architecture, we employed an I2C (Inter Integrated Circuit) communication unit to control the key parameters easily through the personnel computer. Simulation results show that the critical path at the motion estimator is reduced by about 27.47% compared to the conventional structure. As a result, the proposed motion estimator will be applicable for the high-speed frame interpolation of variable video.