The authors developed a portable Japanese text-to-speech system using a pocket-sized formant speech synthesizer. It consists of a linguistic processor and an acoustic processor. The linguistic processor runs on an MS-DOS personal computer and has functions to determine readings and prosodic information for input sentences written in kana-kanji-mixed style. New techniques, such as minimization of a cost function for phrases, rare-compound flag, semantic information, information of reading selection and restriction by associated particles, are used to increase the accuracy of readings and accent positions. The accuracy of determining readings and accent positions is 98.6% for sentences in newspaper articles. It is possible to use the linguistic processor through an interface library which has also been developed by the authors. Consequently, it has become possible not only to convert whole texts stored in text files but also to convert parts of sentences sent by the interface library sequentially, and the readings and prosodic information are optimized for the whole sentence at one time. The acoustic processor is custom-made hardware, and it has adopted new techniques, for the improvement of rules for vowel devoicing, control of phoneme durations, control of the phrase components of voice fundamental frequency and the construction of the acoustic parameter database. Due to the above-mentioned modifications, the naturalness of synthetic speech generated by a Klatt-type formant speech synthesizer was improved. On a naturalness test it was rated 3.61 on a scale of 5 points from 0 to 4.

For the production of high quality synthetic sounds in a text-to-speech system, an excellent synthesizing method of speech signals is indispensable. In this paper, a new speech analysis-synthesis method for the text-to-speech system is proposed. The signals of voiced speech, which have a line spectrum structure at intervals of pitch in the linear frequency domain, can be represented approximately by the superposition of sinusoidal waves. In our system, analysis and synthesis are performed using such a harmonic structure of the signals of voiced speech. In the analysis phase, assuming an exact harmonic structure model at intervals of pitch against the fine structure of the short-time power spectrum, the fundamental frequency f0 is decided so as to minimize the error of the log-power spectrum at each peak position. At the same time, according to the value of the above minimized error, the rate of periodicity of the speech signal is detemined. Then the log-power spectrum envelope is represented by the cosine-series interpolating the data which are sampled at every pitch period. In the synthesis phase, numerical solutions of non-linear differential equations which generate sinusoidal waves are used. For voiced sounds, those equations behave as a group of mutually synchronized oscillators. These sinusoidal waves are superposed so as to reconstruct the line spectrum structure. For voiceless sounds, those non-linear differential equations work as passive filters with input noise sources. Our system has some characteristics as follows. (1) Voiced and voiceless sounds can be treated in a same framowork. (2) Since the phase and the power information of each sinusoidal wave can be easily controlled, if necessary, periodic waveforms in the voiced sounds can be precisely reproduced in the time domain. (3) The fundamental frequency f0 and phoneme duration can be easily changed without much degradation of original sound quality.

Discrete Fourier Transform (DFT) is used for error detection and correction. An iterative decoder is proposed for erasure and impulsive noise which also works with moderate amount of additive random noise. The iterative method is very simple and efficient consisting of modules of Fast Fourier Transforms (FFT) and Inverse FFT's. This iterative decoder can be implemented in a feedback configuration.

For analyzing the transient electromagnetic fields caused by electrostatic discharge (ESD), a new ESD model is presented here. Numerical calculation is also given to explain the distinctive phenomenon being well-recognized in the ESD event.

A text-to-speech conversion system for Japanese has been developed for the purpose of producing high-quality speech output. This system consists of four processing stages: 1) linguistic processing, 2) phonological processing, 3) control parameter generation, and 4) speech waveform generation. Although the processing at the first stage is restricted to the texts on general weather conditions, the other three stages can also cope with texts of news and narrations on other topics. Since the prosodic features of speech are largely related to the linguistic information, such as word accent, syntactic structure and discourse structure, linguistic processing of a wider range than ever, at least a sentence, is indispensable to obtain good quality speech with respect to the prosody. From this point of view, input text was restricted to the weather forecast sentences and a method for linguistic processing was developed to conduct morpheme, syntactic and semantic analyses simultaneously. A quantitative model for generating fundamental frequency contours was adopted to make a good reflection of the linguistic information on the prosody of synthetic speech. A set of prosodic rules was constructed to generate prosodic symbols representing prosodic structures of the text from the linguistic information obtained at the first stage. A new speech synthesizer based on the terminal analog method was also developed to improve the segmental quality of synthetic speech. It consists of four paths of cascade connection of pole/zero filters and three waveform generators. The four paths are respectively used for the synthesis of vowels and vowel-like sounds, nasal murmur and buzz bar, friction, and plosion, while the three generators produce voicing source waveform approximated by polynomials, white Gaussian noise source for fricatives and impulse source for plosives. The validity of the approach above has been confirmed by the listening tests using speech synthesized by the developed system. Improvements both in the quality of prosodic features and in the quality of segmental features were realized for the synthetic speech.

This paper proposes a reconfigurable parallel processor based on a two-dimensional linear celular automaton model. The processor based on the model can be reconfigured quickly by utilizing the characteristics of the automaton used for its model. Moreover, the processor has short data path length between processing elements compared with the length of the processor based on one-dimensional linear cellular automaton model which has been already discussed. The processing elements of the processor based on the two-dimensional linear cellular automaton model are regarded as cells and the operational states of the processor are treated as the states of the automaton. When faults are detected, the processor can be reconfigured by changing its state under the state transition function of the processor determined by the weighting function of the automaton model. The processor can be reconfigured within a clock period required for making a state transition. This processor is extremely effective for real-time data processing systems required high reliability.

A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.

We studied minority carrier collection in high-density stacked-capacitor DRAM cells using a three-dimensional device simulator. We estimated the collected charge for incident angle, location, and junction size and showed that, compared to the conventional structure by a twin-well process, an n-well-guarded cell array fabricated using a triple-well process effectively reduced the charge injected into cells. The reduction was because the n-well absorbed most of the electrons. A so-called "size-effect" did exist and smaller junctions performed better. We concluded that storage capacitance in a 256 M-bit DRAM cell could be reduced, compared to that in previous devices, which would, in turn, help reduce costs in fabricating high-density DRAM.

This paper describes automatic generation of speech synthesis rules which predict a stress level for each bunsetsu in long noun phrases. The rules are inductively inferred from a lot of speech data by using two kinds of tree-based methods, the conventional decision tree and the SBR-tree methods. The rule sets automatically generated by two methods have almost the same performance and decrease the prediction error to about 14 Hz from 23 Hz of the accent component value. The rate of the correct reproduction of the change for adjacent bunsetsu pairs is also used as a measure for evaluating the generated rule sets and they correctly reproduce the change of about 80%. The effectiveness of the rule sets is verified through the listening test. And, with regard to the comprehensiveness of the generated rules, the rules by the SBR-tree methods are very compact and easy to human experts to interpret and matches the former studies.

An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.

New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.

The intensity-dependent transmission characteristics of an Ag+Na+ ion-exchanged glass waveguide with a nematic liquid crystal MBBA cover have been investigated experimentally using an Ar+ laser. It is found that the transmission characteristics of the TE1 mode are strongly influenced by temperature. Optical bistability has been observed at a particular temperature. Such the strong temperature dependence is believed to be brought by an increase in ordinary refractive index of the MBBA cover due to temperature rise.

This paper reports on broad-range wavelength tuning characteristics of DBR lasers which make use of a newly proposed multiple-phase-shift super structure grating (SSG). The reflection characteristics of the SSG reflector are analyzed theoretically. We found that the SSG reflector has periodic sharp reflection peaks each with high reflectivities thus making it a suitable wavelength selective reflector for single-mode lasers. The expected characteristics were evident in multiple-phase-shift SSGs fabricated using a new method which involves multiple-phase-shift insertion. DBR lasers with multiple-phase-shift SSGs were fabricated and their wavelength tuning characteristics were studied. The maximum tuning range is 105 nm in the single longitudinal mode under a CW condition. Dynamic single mode operation was also observed throughout the tuning range.

This paper presents a high-density multiple-valued content-addressable memory (MVCAM) based on a floating-gate MOS device. In the proposed CAM, a basic operation performed in each cell is a threshold function that is a kind of inverter whose threshold value is programmable. Various multiple-valued operations for data retrieval can be easily performed using threshold functions. Moreover, each cell circuit in the MVCAM can be implemented using only a single floating-gate MOS transistor. As a result, the cell area of the four-valued CAM are reduced to 37% in comparison with that of the conventional dynamic CAM cell.

We propose an advanced hyper parallel testing method which improves the line-mode test method by adding data inversion registers which we call the Advanced Line-mode Test (ALT). This testing method has the same testing capability as the conventional bit-by-bit and multi-bit test method (MBT), because it enables the application of a high sensitive and practical test patterns under the hyper parallel condition. The testing time for fixed data patterns are reduced by 1/1900 (all-0/1, checker board, and etc.). Moreover, the ALT can be applicable to the continuous patterns (march, walking, and etc.). The ALT improved from the line-mode test with registers and comparators (LTR) is able to applicable to the most test patterns and to reduce the testing time remarkably, and is suitable for the ULSI memories.

Typical processes controlled by hard real-time computer systems undergo several, mutually exclusive modes of operation. By deterministically switching among a number of static schedules, a pre run-time scheduled system is able to adapt to changing environmental situations. This paper presents concepts for specification of mode changes, construction of static schedules for modes and transitions, and timely run-time execution of mode changes. We propose concepts for mode changes in the context pre run-time scheduled hard real-time systems. While MARS is used to illustrate the concepts' application, they are applicable to a variety of systems. Our methods adhere closely to the ones established for single modes. By decomposing the system into a set of disjoint modes, the design process and its comprehension are facilitated, testing efforts are reduced significantly, and solutions are enabled which do not exist if all system activities of all modes are combined into a single schedule.

This paper proposes a group-to-group communications algorithm that can extend the range of distributed systems where we can achieve active replication fault-tolerance to partner model distributed systems, in which all processes communicate with each other on an equal footing. Active replication approach, in which all replicated processes are active, can achieve fault-tolerance with low overhead because checkhpoint setting and rollback are not required for recovery from process failure. This algorithm guarantees that each replicated process in a process group has the same execution history and that communications between process groups keeps consistency even in the presence of process failure and message loss. The number of control messages that must be transmitted between processes for a communication between process groups is only a linear order of the number of replicated processes in each process group. Furthemore, this algorithm reduces the overhead for reconfiguration of a process group by keeping process failure and recovery information local to each process group.

Space-time tradeoff is a very fundamental issue to design a fault-tolerant real-time (called responsive) system. Routing a message in large computer networks is efficient when each node knows the full topology of the whole network. However, in the hierarchical routing schemes, no node knows the full topology. In this paper, a tradeoff between an optimality of path length (message delay: time) and the amount of topology information (routing table size: space) in each node is presented. The schemes to be analyzed include K-scheme (by Kamoun and Kleinrock), G-scheme (by Garcia and Shacham), and I-scheme (by authors). The analysis is performed by simulation experiments. The results show that, with respect to average path length, I-scheme is superior to both K-scheme and G-scheme, and that K-scheme is better than G-scheme. Additionally, an average path length in I-scheme is about 20% longer than the optimal path length. On the other hand, for the routing table size, three schemes are ranked in reverse direction. However, with respect to the order of size of routing table, the schemes have the same complexity O (log n) where n is the number of nodes in a network.

A responsive network architecture is essential in future open distributed systems. In this paper, a framework that provides the foundations for a responsive network architecture for an internetworking environment is proposed. It is called the Virtually Separated Link (VSL) model. By incorporating this framework, communication of both data and control information can be completed in bounded time. Consequently, a protocol can initiate a recovery mechanism in bounded time, or allow an application to do the same. Its functionalities augment existing resource reservation protocols that support multimedia communication. An overview of a real-time network protocol that is based on this framework is also presented.

Responsive protocols are communication protocols which ensure timely and reliable recovery when error events occur. Protocol synthesis for design of responsive protocols is to derive a protocol specification based on a service specification. In the previous methods, if the service specification includes simultaneous transmission of primitives from a high layer to a low layer through different service access points, then the derived protocol specification includes protocol errors of unspecified reception caused by message collisions. Also, they only includes a recovery function such as retransmission of messages. This is not enough for recovery from abnormal states due to coordination loss. This paper extends a class of derived protocol specifications to include message collisions which usually occur in real communication protocols. Furthermore, this paper proposes a new method for synthesis of a responsive protocal specification derived from a service specification such that the derived protocol specification is free from protocol erros of unspecified receptions caused by message collisions and includes two recovery functions: message retransmission and checkpoint restart functions.