Statistically improved results of power line radiation (PLR) over Eastern Asia observed at 50 and 60Hz are described in this paper. A total number of 150 orbits, which had been observed from June 1984 to January 1986, by the Japanese scientific satellite OHZORA, are used to detect PLR over Eastern Asia around the Japanese Islands. Depending on the increase in the number of data points, the statistical characteristics of the background noise can be precisely determined by using the improved technique compared with the initial analysis. Statistically reasonable data points are detected as PLR based on the +3 criterion, where is the standard deviation of the background noise. Therefore, the statistical reliability for rejecting the background noise is 99.85%. Then, these detected data are applied to the cause-and-effect test. When the statistically detected data points are placed on the map of Eastern Asia, the points cover Eastern Japan and the east coast of China for 50Hz, and they cover Western Japan for 60 Hz. The maps of the detection ratios and those of the average field strengths indicate the positive correlation with the ground maps of the electric power generation at 50 and 60 Hz. The positive correlation is more clearly seen at 50Hz since the background noise is somewhat weaker than that at 60Hz. This close relationship between the satellite observation and the electric power generation suggests that the detection of PLR is not caused by chance, and that PLR penetrates into the ionosphere and propagates approximately just upward. The decrease of field strength with altitude can be interpreted as the gradual decrease of the refractive index from 400 to 700km. Therefore, the detection ratio and the average field strength with respect to the satellite altitude suggest PLR propagating from the bottom of the ionosphere. According to these observational results, it is concluded that PLR in Eastern Asia is high above the high electric power generating regions over Japan and China, and that the satellite observation is capable of estimating PLR field below the ionosphere. These results are the first direct indication that the PLR field is enhanced over the high electric power generation region, and is penetrating into the ionosphere.

In our preceding paper, I-ISMA (Idle Signal Multiple Access for Integrated services), a combination of ISMA and time reservation technique, was proposed to transmit an integrated voice and data traffic in third generation wireless communication networks. There, the channel capacity of I-ISMA was evaluated by the static analysis. To fully estimate performance of contention-based channel access protocols, however, we also need dynamic analysis to evaluate stability, delay, etc. Particularly, in systems concerning real-time voice transmission, delay is one of the most important performance measures. A six-mode model to describe an I-ISMA system is set up. With some assumptions for simplification, the dynamic behavior of the system is approximated by a Markov process so that the EPA (Equilibrium Point Analysis), a fluid approximation method, can be applied to the analysis. Then, numerical and simulation results are obtained for some examples. By means of the same analysis method and under the same conditions, the performance of PRMA is evaluated and compared briefly with that of I-ISMA.

This paper describes a novel method to calculate the fields scattered by a polyhedron structure for an incident plane wave. In this method, the fields diffracted by an edge are calculated using the equivalent edge currents which are separated into components dependent on each of the two surfaces which form the edge. The separated equivalent edge currents are based on the Geometrical Theory of Diffraction (GTD). Using this Separated Equivalent Edge Current Method (SEECM) , fields scattered by a polyhedron structure can be calculated without special treatment of the singularity in the diffraction coefficient. This method can be also applied successfully to structures with convex surfaces by modeling them as polyhedron structures.

This paper proposes a new method of phoneme power control for speech synthesis by rule. The innovation of this method lies in its use of the phoneme environment and the relationship between speech power and pitch frequency. First, the permissible threshold (PT) for power modification is measured by subjective experiments using power manipulated speech material. As a result, it is concluded that the PT of power modification is 4.1 dB. This experimental result is significant when discussing power control and gives a criterion for power control accuracy. Next, the relationship between speech power and pitch frequency is analyzed using a very large speech data base. The results show that the relationship between phoneme power and pitch frequency is affected by the kind of phoneme, the adjoining phonemes, rising or falling pitch, and initial or final position in the sentence. Finally, we propose that the phoneme power should be controlled by pitch frequency and phoneme environment. This proposal is implemented in a waveform concatenation type text-to-speech synthesizer. This new method yields an averaged root mean square error between real and estimated speech power of 2.17 dB. This value indicates that 94% of the estimated power values are within the permissible threshold of human perception.

The design of a high speed self-routing network switch module is described. Clock distribution and timing design to achieve high-speed operation are considered. A 88-port self-routing Benes network switch prototype on multi-chip module is fabricated using 44-port space division switch LSIs. The switch module achieves a maximum measured clock frequency of 750MHz under switching operation. Resultant total throughput of the switch module is 12Gbit/s.

The semiconductor technology has been progressing with a rate of 4 times per every 3 years, and the semiconductor industry has been expanding with the annual growth rate of around 14% in average. Recently, however, the situation seems to be somewhat changing. This paper investigates the trends in the past of VLSI technologies and performances of VLSI chips, of the R & D and equipment investments, and of the production and design costs. By extrapolating these trends, the future prospects for VLSIs are given in both the technology and the economics. According to these prospects, (1) 1 Gbit DRAMs and 50 M transistor system VLSIs would be realized before 2000, (2) investments for R & D and production equipments will steeply increase up to the unreasonable value, and (3) the delay in demand will become longer, which will make the return on investment difficult. As some of the key issues for overcoming these difficulties, the reduction in the investment and the cost,the alliance, and the market creation are discussed.

This paper describes automatic generation of speech synthesis rules which predict a stress level for each bunsetsu in long noun phrases. The rules are inductively inferred from a lot of speech data by using two kinds of tree-based methods, the conventional decision tree and the SBR-tree methods. The rule sets automatically generated by two methods have almost the same performance and decrease the prediction error to about 14 Hz from 23 Hz of the accent component value. The rate of the correct reproduction of the change for adjacent bunsetsu pairs is also used as a measure for evaluating the generated rule sets and they correctly reproduce the change of about 80%. The effectiveness of the rule sets is verified through the listening test. And, with regard to the comprehensiveness of the generated rules, the rules by the SBR-tree methods are very compact and easy to human experts to interpret and matches the former studies.

Computing devices have reached data frequencies of 100 MHz, and have created a need for small-amplitude impedance-matched buses. We simulated signal transmission characteristics of two basic driver circuits, push-pull and open-drain,for a synchronous DRAM I/O bus. The push-pull driver caused less signal distortion with parasitic inductance and capacitance of packages, and thus has higher frequency limits than the open-drain GTL type. We describe a bus system using push-pull drivers which operates at over 125 MHz. The bus line is 70 cm with 8 I/O loads distributed along the line, each having 25 nH7pF parasitic inductance and capacitance.

Multiplication-accumulation is the basic computation required for image filtering operations. For real-time image filtering, very high throughput computation is essential. This work proposes a hardware algorithm for an application-specific VLSI architecture which realizes an area-efficient high throughput multiplier-accumulator. The proposed algorithm utilizes a priori knowledge of filter mask coefficients and optimizes number of basic hardware components (e.g., full adders, pipeline latches, etc.). This results in the minimum area VLSI architecture under certain input/output constraints.

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.

This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns.

A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.

We deal with a new type ceramic emitter which is used in a cleanroom ionizer system and is composed of a needle-shaped silicon and a rod-shaped silicon carbide ceramics. The discharge test was carried out to investigate the particle generation from the emitter and the degradation of the emitter. As a result, it was found that the ceramic emitter had practically higher performance than a conventional tungsten emitter.

To realize Broadband ISDN, which provides multi-media services, ATM (Asynchronous Transfer Mode) has been standardized by CCITT and the development of the system is accelerating towards the 21st century. The packet-oriented information transfer based on fixed size blocks called cells provides a very flexible allocation of transmission capacity to different connections. On the other hand, to ensure the QoS (Quality of Service) for all established connections it is necessary to monitor and regulate the input traffic from each user based on usage parameters which are negotiated between user and network at connection set-up, i.e., a policing function is required. In this paper some requirements for a policing function will be given. Accuracy of the policing decision for violating and well-behaving sources, tolerance with respect to cell delay variation (CDV) which is caused by multiplexing functions between the source terminal and the policing device, time to detect arriving violating cells, implementation complexity, and amount, i.e., cost effectiveness, are discussed mainly. We present simulation results for five policing mechanisms, Leaky Bucket (LB), Jumping Window (JW), and Moving Window (MW) which have been already well-known, Pseudo Jumping Window (PJW), and Pseudo Moving Window (PMW) which are proposed mechanisms. PJM and PMW mechanisms required a pseudo cell buffer with finite queueing capacity to the corresponding JW and MW mechanisms, respectively. These two mechanisms can be expected as advanced methods from view points of the accuracy of the policing for long-term fluctuated compliant source, fast reaction ability and restrictness to long burst traffic comparing with the above existing methods. We compare the five mechanisms based on the above requirements and show that the PJW and the LB are the most effective mechanisms for mean rate policing in ATM networks.

High Definition Television (HDTV) is likely to be one of the major services in the Broadband Integrated Services Digital Network (B-ISDN). The transmission of HDTV signals on digital networks requires the adoption of sophisticated compression techniques to limit the bit-rate requirements and to provide high-quality and cost-effective network services. A flexible coding scheme that supports various bit-rates is needed to support the various services expected which will have different requirements. This paper describes the design of an HDTV codec based on a subband DCT coding algorithm that can encode original 1.2 Gb/s HDTV signals to less than 50Mb/s. A configuration that efficiently bridges HDTV and standard TV signals is also proposed. Computer simulation results show that the degradation caused by the bridging function is insignificant. In the coder, first stage quadrature mirror filters (QMFs) decompose the input signal into two bands in the horizontal direction, while the second stage filters decompose the two bands into four bands in the vertical direction. Adaptive DCT (Discrete Cosine Transform) is adopted for horizontal-low and vertical-low (LL) signal coding. High-band signals are coded by adaptive DPCM and PCM. To maximize bit-rate reduction efficiency, DCT coding is adaptively applied to either the intra-field signals, the inter-field signals, or the motion compensated inter-frame signals. Bi-directional inter-frame prediction is applied to the adaptive DCT coding to improve coding performance at low bit rates. The same prediction mode as for LL signal is applied to adaptive DPCM coding of LH and HL signals. Compatibility is realized by a configuration in which both the TV signal components and the residual signal, derived by subtracting the TV signal from the LL signal, are encoded.

Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 µm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 5125128 pixels basis screen, with a clear mode of 4.6 GByte/sec and a 4-multi column write mode of 400 MByte/sec, even using the same 0.8 µm technology as the previous VRAM (1 Mb) was realized.

We studied minority carrier collection in high-density stacked-capacitor DRAM cells using a three-dimensional device simulator. We estimated the collected charge for incident angle, location, and junction size and showed that, compared to the conventional structure by a twin-well process, an n-well-guarded cell array fabricated using a triple-well process effectively reduced the charge injected into cells. The reduction was because the n-well absorbed most of the electrons. A so-called "size-effect" did exist and smaller junctions performed better. We concluded that storage capacitance in a 256 M-bit DRAM cell could be reduced, compared to that in previous devices, which would, in turn, help reduce costs in fabricating high-density DRAM.

This paper presents a parallel sorting algorithm which sorts n elements on O(n/w+n log n/p) time using p(n) processors arranged in a 1-dimensional grid with w(n1-ε) buses for every fixed ε>0. Furthermore, it is shown that np elements can be sorted in O(n/w+n log n/p) time on pp (pn) processors arranged in a 2-dimensional grid with w(n1-ε) buses in each column and in each row. These algorithms are optimal because their time complexities are equal to the lower bounds.

For analyzing the transient electromagnetic fields caused by electrostatic discharge (ESD), a new ESD model is presented here. Numerical calculation is also given to explain the distinctive phenomenon being well-recognized in the ESD event.