The concept of functional memory was proposed over nearly four decades ago. However, the actually usable products have not appeared until the 1980s instead of the long history of development. Functional memory is classified into three categories; there are a general functional memory, a processing element array with small size memory and a special purpose memory. Today a majority of functional memory is an associative memory or a content addressable memory (CAM) and a special purpose memory based on CAM. Due to advances in fablication capability,the capacity of CAM LSI has increased over 100 K bits. A general purpose CAM was developed based on SRAM cell and DRAM cell, respectively. The typical CAM LSI of both types, 20 K bits SRAM based CAM and 288 K bits DRAM based CAM, are introduced. DRAM based CAM is attractive for the large capacity. A parallel processor architecture based on CAM cell is proposed which is called a Functional Memory Type Parallel Processor (FMPP). The basic feature is a dual character of a higher performance CAM and a tiny processor array. It can perform a highly parallel operation to the stored data.

We deal with a new type ceramic emitter which is used in a cleanroom ionizer system and is composed of a needle-shaped silicon and a rod-shaped silicon carbide ceramics. The discharge test was carried out to investigate the particle generation from the emitter and the degradation of the emitter. As a result, it was found that the ceramic emitter had practically higher performance than a conventional tungsten emitter.

The paper indicates the importance of suitability assesment in speech synthesis applications. Human factors involved in the use of a synthetic speech are first discussed on the basis of an example of a newspaper company where synthetic speech is extensively used as an aid for proofreading a manuscript. Some findings obtained from perceptual experiments on the subjects' preference for paralinguistic properties of synthetic speech are then described, focusing primarily on the suitability of pitch characteristics, speaker's gender, and speaking rates in the task where subjects are asked to proofread a printed text while listening to the speech. The paper finally claims the need for a flexibile speech synthesis system which helps the users create their own synthetic speech.

A new concept for a positioning satellite system based on a new satellite constellation has been studied. The system needs a minimum of four satellites injected into quasi-geostationary orbit (QGEO) with high inclination. Due to the QGEO characteristic, the satellites are orbiting within continuous visibility range of ground control stations (GCS), from which the satellite time is controlled through the link connections of the feeder and the intersatellite communication (ISC). Consideration is made for the required high accuracy and quality checks against malfunction, wherever the satellites may be positioned. The orbit data processing function, another major function, is performed independently of the time control. The case of global coverage attained by twelve satellites has been studied in this paper. When a constellation of satellites for a global navigation satellite system (GNSS) is designed, conditions to obtain a good geometric dilution of precision (GDOP) at all places and times should be considered. Therefore, the satellites will be spread out in wide directions and are in an asymmetrical arrangement when seen by an observer are considered when setting the parameters of the ephemerides of the constellation. Under the restraints of the designed constellation, the GDOP value distribution for a third of the world map with area time parameters is computed and summarized in histograms for the system evaluation.

This paper proposes a reconfigurable parallel processor based on a two-dimensional linear celular automaton model. The processor based on the model can be reconfigured quickly by utilizing the characteristics of the automaton used for its model. Moreover, the processor has short data path length between processing elements compared with the length of the processor based on one-dimensional linear cellular automaton model which has been already discussed. The processing elements of the processor based on the two-dimensional linear cellular automaton model are regarded as cells and the operational states of the processor are treated as the states of the automaton. When faults are detected, the processor can be reconfigured by changing its state under the state transition function of the processor determined by the weighting function of the automaton model. The processor can be reconfigured within a clock period required for making a state transition. This processor is extremely effective for real-time data processing systems required high reliability.

A stored channel simulator for digital mobile radio enviroments is proposed, which enables the field tests in the laboratory under identical conditions, since it can reproduce the actual multipath radio channels by using the channel impulse responses (CIR's) measured in the field. Linear interpolation of CIR is introduced to simplify the structure of the proposed simulator. The performance of the proposed simulator is confirmed by the laboratory tests.

High Definition Television (HDTV) is likely to be one of the major services in the Broadband Integrated Services Digital Network (B-ISDN). The transmission of HDTV signals on digital networks requires the adoption of sophisticated compression techniques to limit the bit-rate requirements and to provide high-quality and cost-effective network services. A flexible coding scheme that supports various bit-rates is needed to support the various services expected which will have different requirements. This paper describes the design of an HDTV codec based on a subband DCT coding algorithm that can encode original 1.2 Gb/s HDTV signals to less than 50Mb/s. A configuration that efficiently bridges HDTV and standard TV signals is also proposed. Computer simulation results show that the degradation caused by the bridging function is insignificant. In the coder, first stage quadrature mirror filters (QMFs) decompose the input signal into two bands in the horizontal direction, while the second stage filters decompose the two bands into four bands in the vertical direction. Adaptive DCT (Discrete Cosine Transform) is adopted for horizontal-low and vertical-low (LL) signal coding. High-band signals are coded by adaptive DPCM and PCM. To maximize bit-rate reduction efficiency, DCT coding is adaptively applied to either the intra-field signals, the inter-field signals, or the motion compensated inter-frame signals. Bi-directional inter-frame prediction is applied to the adaptive DCT coding to improve coding performance at low bit rates. The same prediction mode as for LL signal is applied to adaptive DPCM coding of LH and HL signals. Compatibility is realized by a configuration in which both the TV signal components and the residual signal, derived by subtracting the TV signal from the LL signal, are encoded.

A terminal-analog synthesizer which uses a glottal model has already been proposed for rule-based speech synthesis, but the control strategy for glottal source intensity levels has not yet been defined. On the other hand, power-control rules which determine the target segmental power of synthetic speech have been proposed, based on statistical analysis of the power in natural speech. It is pointed out that there is a close correlation between observed fundamental frequency and power levels in natural speech; however, the theoretical reasons for this correlation have not been explained. This paper shows the relationship between fundamental frequency and resultant power in a terminal-analog synthesizer which uses a glottal model. From the equations it can be deduced that the tendency in natural speech for power to increase with fundamental frequency can be closely simulated by the sum of the effect of the radiation characteristic and the effect of the synthesis system's vocal tract transfer function. In addition, this paper proposes a method for adjusting the power of synthetic speech to any desired value. This control method can be executed in real-time.

This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns.

Computing devices have reached data frequencies of 100 MHz, and have created a need for small-amplitude impedance-matched buses. We simulated signal transmission characteristics of two basic driver circuits, push-pull and open-drain,for a synchronous DRAM I/O bus. The push-pull driver caused less signal distortion with parasitic inductance and capacitance of packages, and thus has higher frequency limits than the open-drain GTL type. We describe a bus system using push-pull drivers which operates at over 125 MHz. The bus line is 70 cm with 8 I/O loads distributed along the line, each having 25 nH7pF parasitic inductance and capacitance.

A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.

We studied minority carrier collection in high-density stacked-capacitor DRAM cells using a three-dimensional device simulator. We estimated the collected charge for incident angle, location, and junction size and showed that, compared to the conventional structure by a twin-well process, an n-well-guarded cell array fabricated using a triple-well process effectively reduced the charge injected into cells. The reduction was because the n-well absorbed most of the electrons. A so-called "size-effect" did exist and smaller junctions performed better. We concluded that storage capacitance in a 256 M-bit DRAM cell could be reduced, compared to that in previous devices, which would, in turn, help reduce costs in fabricating high-density DRAM.

The semiconductor technology has been progressing with a rate of 4 times per every 3 years, and the semiconductor industry has been expanding with the annual growth rate of around 14% in average. Recently, however, the situation seems to be somewhat changing. This paper investigates the trends in the past of VLSI technologies and performances of VLSI chips, of the R & D and equipment investments, and of the production and design costs. By extrapolating these trends, the future prospects for VLSIs are given in both the technology and the economics. According to these prospects, (1) 1 Gbit DRAMs and 50 M transistor system VLSIs would be realized before 2000, (2) investments for R & D and production equipments will steeply increase up to the unreasonable value, and (3) the delay in demand will become longer, which will make the return on investment difficult. As some of the key issues for overcoming these difficulties, the reduction in the investment and the cost,the alliance, and the market creation are discussed.

The finite-difference beam-propagation method is applied to the analysis of hollow slab waveguides (HSWs). The attenuation constants for the TE0 and TE1 modes are evaluated and compared with those obtained by the perturbation theory. The propagating field and differential power loss in the transition from a straight HSW to a bent HSW are revealed and discussed.

We propose a smart design methodology for advanced ULSI memories to reduce the turn around time(TAT) for circuit revisions with no area penalty. This methodology was executed by distributing extra gate-arrays, which were composed of the n-channel and p-channel transistors, under the power line and the signal line. This method was applied to the development of a 16 Mb DRAM with double metal wiring. The design TAT can be reduced to 1/8 using 1500 gates. This design methodology has been confirmed to be very effective.

A quick evaluation method is proposed to obtain stability robustness measures in polynomial coefficient space based on knowledge of coefficients of a Hurwitz stable nominal polynomial. Two norms are employed: l- and l2-norm, which correspond to the stability hypercube and hyperball in the space, respectively. Just inverting Hurwitz matrix for the nominal polynomial immediately yields closed-form estimates for the size of the hypercube and hyperball.

To make a fast Bi-CMOS SRAM yield high without speed degradation, three defect-repair methods, the address comparison method, the fuse decoder method and the distributed fuse method, were considered in detail and their advantages and disadvantages were made clear. The distributed fuse method is demonstrated to be further improved by a built-in fuse word driver and a built-in fuse column selector, and fuse analog switches. This enhanced distributed fuse scheme was examined in a fast Bi-CMOS SRAM. A maximun access time of 14 ns and a chip size of 8.8 mm17.4 mm are expected for a 4 Mb Bi-CMOS SRAM in the future.

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.