This paper presents our investigation of non-orthogonal multiple access (NOMA) as a novel and promising power-domain user multiplexing scheme for future radio access. Based on information theory, we can expect that NOMA with a successive interference canceller (SIC) applied to the receiver side will offer a better tradeoff between system efficiency and user fairness than orthogonal multiple access (OMA), which is widely used in 3.9 and 4G mobile communication systems. This improvement becomes especially significant when the channel conditions among the non-orthogonally multiplexed users are significantly different. Thus, NOMA can be expected to efficiently exploit the near-far effect experienced in cellular environments. In this paper, we describe the basic principle of NOMA in both the downlink and uplink and then present our proposed NOMA scheme for the scenario where the base station is equipped with multiple antennas. Simulation results show the potential system-level throughput gains of NOMA relative to OMA.

This paper investigates the system-level throughput of non-orthogonal multiple access (NOMA) with a successive interference canceller (SIC) in the cellular downlink assuming proportional fair (PF)-based radio resource (bandwidth and transmission power) allocation. The purpose of this study is to examine the possibility of applying NOMA with a SIC to the systems beyond the 4G cellular system. Both the mean and cell-edge user throughput are important in a real system. PF-based scheduling is known to achieve a good tradeoff between them by maximizing the product of the user throughput among users within a cell. In NOMA with a SIC, the scheduler allocates the same frequency to multiple users simultaneously, which necessitates multiuser scheduling. To achieve a better tradeoff between the mean and cell-edge user throughput, we propose and compare three power allocation strategies among users, which are jointly implemented with multiuser scheduling. Extensive simulation results show that NOMA with a SIC with a moderate number of non-orthogonally multiplexed users significantly enhances the system-level throughput performance compared to orthogonal multiple access (OMA), which is widely used in 3.9 and 4G mobile communication systems.

Highly accurate pedestrian position information is required in many applications, especially in automatic driving system. Global Positioning System (GPS) developed by American has proven itself reliability in most of the environments. Unfortunately, urban areas contain the signal reflection, known as multipath and non-line-of-sight (NLOS) effects. In addition, the lake of line-of-sight (LOS) satellites caused by the blockage of skyscrapers also severely degrades the accuracy and availability of the GPS positioning. To solve these problems, a solution that interoperated several Global Navigation Satellite Systems (GNSSs) is proposed. However, the actual difficulty of satellite positioning in urban area is the distorted satellite distribution. This paper proposes a GPS with 3D map ray tracing positioning method to conquer the difficulty. The proposed method takes the advantage of the non-LOS (NLOS) and uses it as an additional measurement. Significantly, these measurements are sourced from the satellites that should be blocked. Thus, the dilution of precision (DOP) can be greatly improved. To verify the performance of the proposed method, real data is collected at Tokyo urban area. This paper compares the performance of GPS/GLONASS and the proposed GPS with 3D map ray tracing methods. The results reveals the proposed method is capable of identifying which side of street the pedestrian stands and the GPS+GLONASS method is not.

We propose a novel phased array-fed dual-reflector antenna that reduces performance degradation caused by multiple reflection. The marked feature of the proposed configuration is that different reflector profiles are employed for the two orthogonal directions. The reflector profile in the beam-scanning section (vertical section) is set to an imaging reflector configuration, while the profile in the orthogonal non-beam-scanning section (horizontal section) is set to a ring-focus Cassegrain antenna configuration. In order to compare the proposed antenna with the conventional antenna in which multiple reflection was problematic, we designed a prototype antenna of the same size, and verified the validity of the proposed antenna. The results of the verification were that the gain in the designed central frequency increased by 0.4 dB, and the ripple of the gain frequency properties that was produced by multiple reflection was decreased by 1.1,dB. These results demonstrated the validity of the proposed antenna.

The joint power allocation (PA) issue is studied in multi-user three-cell systems under the degree-of-freedom (DoF) based transmission protocol. This protocol makes all the interferences received at each user orthogonal to the useful signal at the same user by Jafar's topological interference management through index coding, which is proved to offer full DoF. Under this protocol, we formulate the joint power allocations problem based on the objective of energy efficiency under the required quality-of-service constraint. Due to the highly complicated Lagrangian equation, the properties of Lambert function are widely exploited to solve the problem using a closed-form expression. It is discovered that the relationship among the optimal power coefficients are completely different from that of the well-known water-filling method. Simulations demonstrate the energy efficiency of the designed scheme.

LED (Light Encryption Device) block cipher, one of lightweight block ciphers, is very compact in hardware. Its encryption process is composed of AES-like rounds. Recently, a scan-based side-channel attack is reported which retrieves the secret information inside the cryptosystem utilizing scan chains, one of design-for-test techniques. In this paper, a scan-based attack method on the LED block cipher using scan signatures is proposed. In our proposed method, we focus on a particular 16-bit position in scanned data obtained from an LED LSI chip and retrieve its secret key using scan signatures. Experimental results show that our proposed method successfully retrieves its 64-bit secret key using 36 plaintexts on average if the scan chain is only connected to the LED block cipher. These experimental results also show the key is successfully retrieved even if the scan chain includes additional 130,000 1-bit data.

This paper presents an adaptive feedback canceller (AFC) based on a pseudo affine projection (PAP) algorithm that can provide fast and stable adaptation to the time-varying environment. The proposed algorithm utilizes the adaptive linear prediction (LP) to obtain the LP coefficients of input signal model and the inverse gain filter (IGF) to alleviate the effect of compensation gain. As a result, when the input is model as an AR signal, the proposed algorithm satisfies the condition for having an almost unbiased estimatie of the feedback path and then its performance is relatively independent of the gain setting of hearing aids. Simulation results showed that the proposed algorithm is capable of obtaining unbaised feedback path estimates and high speech quality.

Sound source localization (SSL), with a binaural input in practical environments, is a challenging task due to the effects of noise and reverberation. In psychoacoustic research field, one of the theories to explain the mechanism of human perception in such environments is the well-known equalization-cancellation (EC) model. Motivated by the EC theory, this paper investigates a binaural SSL method by integrating EC procedures into a beamforming technique. The principle idea is that the EC procedures are first utilized to eliminate the sound signal component at each candidate direction respectively; direction of sound source is then determined as the direction at which the residual energy is minimal. The EC procedures applied in the proposed method differ from those in traditional EC models, in which the interference signals in rooms are accounted in E and C operations based on limited prior known information. Experimental results demonstrate that our proposed method outperforms the traditional SSL algorithms in the presence of noise and reverberation simultaneously.

With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.

The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking,vector-masking) to block them from reaching the multiple-input signature register(MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.

Binaural reproduction is one of the promising approaches to present a highly realistic virtual auditory space to a listener. Generally, binaural signals are reproduced using a set of headphones that leads to a simple implementation of such a system. In contrast, binaural signals can be presented to a listener using a technique called “transaural reproduction” which employs a few loudspeakers with crosstalk cancellation for compensating acoustic transmissions from the loudspeakers to both ears of the listener. The major advantage of transaural reproduction is that a listener is able to experience binaural reproduction without wearing any device. This leads to a more natural listening environment. However, in transaural reproduction, the listener is required to be still within a very narrow sweet spot because the crosstalk canceller is very sensitive to the listener's head position and orientation. To solve this problem, dynamic transaural systems have been developed by utilizing contact type head tracking. This paper introduces the development of a dynamic transaural system with non-contact head tracking which releases the listener from any attachment, thereby preserving the advantage of transaural reproduction. Experimental results revealed that sound images presented in the horizontal and median planes were localized more accurately when the system tracked the listener's head rotation than when the listeners did not rotate their heads or when the system did not track the listener's head rotation. These results demonstrate that the system works effectively and correctly with the listener's head rotation.

Most existing outlier detection algorithms only utilized location of trajectory points and neglected some important factors such as speed, acceleration, and corner. To address this problem, we present a Trajectory Outlier Detection algorithm based on Multi-Factors (TODMF). TODMF is improved in terms of distance-based outlier detection algorithms. It combines multi-factors into outlier detection to find more meaningful trajectory outliers. We resort to Canonical Correlation Analysis (CCA) to optimize the number of factors when determining what factors will be considered. Finally, the experiments with real trajectory data sets show that TODMF performs efficiently and effectively when applied to the problem of trajectory outlier detection.

This paper proposes a new address method to reduce the address power consumption in an AC plasma panel display (AC-PDP). We apply an overlap scan method, in which the scan pulse overlaps with those of the previous scan time and the next scan time. The overlap scan method decreases the address voltage and consequently reduces the address power consumption. However, the drawback of this method is the narrow address voltage margin. This occurs because the maximum address voltage decreases much more than the minimum address voltage does. In order to increase the address voltage margin, we apply a two-step address voltage waveform, in the overlap scan method. In this case, the maximum address voltage increases; however, the minimum address voltage is almost the same. This leads to a wide address voltage margin. Moreover, the two-step address voltage waveform reduces the address power consumption, because the address voltage rises and falls in two steps using an energy recovery capacitor. Consequently, the experimental results show that the new address method reduces the address power consumption by 19.6,Wh (58%) when compared with the conventional method.

Trivium is a synchronous stream cipher using three shift registers. It is designed to have a simple structure and runs at high speed. A scan-based side-channel attack retrieves secret information using scan chains, one of design-for-test techniques. In this paper, a scan-based side-channel attack method against Trivium using scan signatures is proposed. In our method, we reconstruct a previous internal state in Trivium one by one from the internal state just when a ciphertext is generated. When we retrieve the internal state, we focus on a particular 1-bit position in a collection of scan chains and then we can attack Trivium even if the scan chain includes other registers than internal state registers in Trivium. Experimental results show that our proposed method successfully retrieves a plaintext from a ciphertext generated by Trivium.

Negative Bias Temperature Instability (NBTI) is one of the serious concerns for long-term circuit performance degradation. NBTI degrades PMOS transistors under negative bias, whereas they recover once negative bias is removed. In this paper, we propose a mitigation method for NBTI-induced performance degradation that exploits the recovery property by shifting random input sequence through scan paths. With this method, we prevent consecutive stress that causes large degradation. Experimental results reveal that random scan-in vectors successfully mitigate NBTI and the path delay degradation is reduced by 71% in a test case when standby mode occupies 10% of total time. We also confirmed that 8-bit LFSR is capable of random number generation for this purpose with low area and power overhead.

The parallel interference cancellation (PIC) multiple input multiple output (MIMO) detection algorithm has bit error ratio (BER) performance comparable to the maximum likelihood (ML) algorithm but with complexity close to the simple linear detection algorithm such as zero forcing (ZF), minimum mean squared error (MMSE), and successive interference cancellation (SIC), etc. However, the throughput of PIC MIMO detector on central processing unit (CPU) cannot meet the requirement of wireless protocols. In order to reach the throughput required by the standards, the graphics processing unit (GPU) is exploited in this paper as the modem processor to accelerate the processing procedure of PIC MIMO detector. The parallelism of PIC algorithm is analyzed and the two-stage PIC detection is carefully developed to efficiently match the multi-core architecture. Several optimization methods are employed to enhance the throughput, such as the memory optimization and asynchronous data transfer. The experiment shows that our MIMO detector has excellent BER performance and the peak throughput is 337.84 Mega bits per second (Mbps), about 7x to 16x faster than that of CPU implementation with SSE2 optimization methods. The implemented MIMO detector has better computing throughput than recent GPU-based implementations.

This paper addresses the problems of fingerprint identification and verification when a query fingerprint is taken under conditions that differ from those under which the fingerprint of the same person stored in a database was constructed. This occurs when using a different fingerprint scanner with a different pressure, resulting in a fingerprint impression that is smeared and distorted in accordance with a geometric transformation (e.g., affine or even non-linear). Minutiae points on a query fingerprint are matched and aligned to those on one of the fingerprints in the database, using a set of absolute invariants constructed from the shape and/or size of minutiae triangles depending on the assumed map. Once the best candidate match is declared and the corresponding minutiae points are flagged, the query fingerprint image is warped against the candidate fingerprint image in accordance with the estimated warping map. An identification/verification cost function using a combination of distance map and global directional filterbank (DFB) features is then utilized to verify and identify a query fingerprint against candidate fingerprint(s). Performance of the algorithm yields an area of 0.99967 (perfect classification is a value of 1) under the receiver operating characteristic (ROC) curve based on a database consisting of a total of 1680 fingerprint images captured from 240 fingers. The average probability of error was found to be 0.713%. Our algorithm also yields the smallest false non-match rate (FNMR) for a comparable false match rate (FMR) when compared to the well-known technique of DFB features and triangulation-based matching integrated with modeling non-linear deformation. This work represents an advance in resolving the fingerprint identification problem beyond the state-of-the-art approaches in both performance and robustness.

A high-speed and low-power 8-bit subranging analog-to-digital converter (ADC) based on 65-nm CMOS technology was fabricated. Rather than using digital foreground calibration, an analog-centric approach was adopted to reduce power dissipation. An offset cancelling charge-steering amplifier and capacitive-averaging technique effectively reduce the offset, noise, and power dissipation of the ADC. Moreover, the circuit used to compensate the kickback noise current from the comparator can also reduce the power dissipation. The reference-voltage generator for the fine ADC is composed of a fine ladder and a capacitor providing an AC signal path. This configuration reduces the power dissipation of the selection signal drivers for the analog multiplexer. A test chip fabricated using 65-nm digital CMOS technology achieved a high sampling rate of 1GHz, a low power dissipation of 17.5mW, and a figure of merit of 118fJ/conv.-step.

We propose a new Bloom filter that efficiently filters out non-members. With extra bits assigned and asymmetrically distributed, the new filter reduces hash computations and memory accesses. For an error rate of 10-6, the new filter reduces cost by 31.31% with 4.33% additional space, while the standard method saves offers a 20.42% reduction.

A 7bit 1GS/s flash ADC using two bit active interpolation and background offset calibration is proposed and tested. It achieves background calibration using 36 pre-amplifiers with 139 comparators. To cancel the offset, two pre-amplifiers and 12 comparators are set to offline in turn while the others are operating. A two bit active interpolation design and an offset cancellation scheme are implemented in the latch stage. The interpolation and background calibration significantly reduce analog input signal as well as reference voltage load. Fabricated with the 90nm CMOS process, the proposed ADC consumes 95mW under a 1.2V power supply.