We present a novel burst-mode transimpedance amplifier (TIA) with a gain-mode switching. The proposed TIA utilizes a regulated-cascode (RGC) input stage for broadband characteristics. To expand a dynamic range, the RGC controls a linear operating range depending on transimpedance gains by adjusting bias conditions. This TIA is implemented using the 0.18μm-CMOS technology. The experimental results show that the proposed TIA IC has a good eye-opening and can respond quickly to the burst data.

A microwave power amplifier with independently biased InGaP/GaAs HBTs is proposed, and its superior performance is confirmed. Using harmonic balance simulation, the optimal bias conditions for an amplifier with two independently biased InGaP/GaAs HBTs were investigated with the aim of achieving high-efficiency low-distortion performance. A 1.9-GHz-band cascode power amplifier was designed and fabricated. Power efficiencies and third-order intermodulation distortions (IMD3) for the fabricated amplifier were estimated. The collector bias voltage of the first stage transistor mainly affects power-added efficiency (PAE). The base bias current of the first-stage HBT mainly affects IMD3 characteristics, and that of the second-stage HBT mainly affects PAE. The proposed amplifier shows superior performance when compared to a conventional cascode amplifier. The amplifier achieved a maximum PAE of 68.0% with an output power of 14.8dBm, and IMD3 better than -35dBc with a PAE of 25.1%, for a maximum output power of 10.25dBm at 1.9GHz. A PAE of more than 60% was achieved from 1.87 to 1.98GHz.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm2.

In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.

This Paper presents the design of a wideband variable gain amplifier (VGA) using 0.18 µm standard CMOS technology. The proposed VGA realizes wideband flat gain using wideband flat negative capacitance. It achieves a 3 dB gain bandwidth of 1 GHz with a maximum gain of 23 dB. Also, it shows P1 dB of -33 to -6 dBm over the gain range of -28 to 23 dB. The overall current consumption is 5.5 mA under a 1.5 V supply.

This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.

This paper describes a broadband active terminal circuit and its application to a distributed amplifier. In this study, we first analyzed and compared three types of active terminal circuits using representative circuit configurations, namely, an active terminal circuit with a common-emitter BJT, an active terminal circuit with a Darlington BJT pair, and an active terminal circuit with cascode-connected BJTs. The simulation results showed that the active terminal circuit with cascode-connected BJTs kept the matching condition up to high frequency. After the simulation, we fabricated a distributed amplifier that used an active terminal circuit with cascode-connected BJTs. The RF amplifier achieved a flat gain of 9.7 1.0 dB over a range of 3-15 GHz.

In this paper, a new operational amplifier is presented that improves the specifications such as dc gain, common mode rejection ratio. To obtain these improvements, we have used the two important concepts of feedback and bulk amplification.

This paper presents a novel gain boosted and bandwidth enhanced CMOS Op-Amp based on the well-known folded cascode structure. In contrast with the conventional methods which increase output resistance for gain boosting, the transconductance of the circuit is increased, therefore the -3 dB frequency is the same as for folded cascode structure. With negligible extra power consumption, the unity gain bandwidth is increased considerably. In this method, a new node is created in the circuit which introduces a pole to the transfer function with a frequency lower than cascode pole; feed-forward compensation is employed to reduce the effect of this pole on the frequency response. The input common mode range is limited slightly by 0.2-0.3 V with respect to folded cascode which is insensible. HSPICE simulations using level 49 parameters (BSIM3v3) in a typical 0.35 µm CMOS technology result in three times gain boosting and 60% enhancement in unity gain bandwidth compared to folded cascode, while the power consumption is increased by 10%.

This paper presents a cascode-pair distributed amplifier design approach using 0.25 µm GaAs-based PHEMT MMIC technology, which covers 2-32 GHz. Electromagnetic simulation results show that this amplifier achieves 18 dB gain from 2 to 32 GHz and 0.5 dB gain flatness over the band. The reflected coefficients at the input and output ports are below -10 dB up to 27 GHz. The output power at 1 dB compression is greater than 24 dBm at 20 GHz. An appropriate feedback resistance can be utilized to improve P1 dB for about 6 dBm. The DOE (design of experiment) approach is carried out by a simulation tool for better performance and tolerance of the devices is also analyzed. The circuit configuration is capable of operating over ultra-broad band amplification.

This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hybrid cascode compensation are about 40 percent greater than those of the conventional cascode compensation. Circuit level simulation results are provided to show the accuracy of the calculated expressions and also the usefulness of the proposed cascode compensation technique.

In the design of cascode CMOS low-noise amplifiers, the gate-drain capacitance is generally neglected because it is thought to be small enough compared to gate-source capacitance. However, a careful examination will reveal the fact that the drain impedance of the input transistor significantly affects the input impedance through the gate-drain capacitance, especially as the CMOS technology getting more and more advanced. Moreover, the substrate coupling network of the input transistor also comes into play when the drain impedance of the input transistor is high enough compared to the substrate coupling network. In order to make input matching easier, it is desirable to know the details of the substrate coupling network. Unfortunately, designers generally do not have enough information about the technology they have used, not to mention knowing the details concerning the substrate coupling network. As a matter of fact, designers generally do have foundry provided component models that contain information about the substrate coupling network. This gives us the chance to minimize its effect and predict the input impedance of a low noise amplifier more accurately. In this paper, we show that the effect of the substrate coupling network can be ignored by keeping the drain impedance of the input transistor low enough and a proper drain impedance can then be chosen to achieve input matching without the need of iteration steps. Simulation results of a 2.4 GHz CMOS low noise amplifier using foundry provided component models are also presented to demonstrate the validation of the proposed input matching method.

This article describes a large bandwidth and low distortion line driver in a 0.35-µm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.

A novel delta-sigma modulator that utilizes a resonant-tunneling diode (RTD) quantizer is proposed and its operation is investigated by HSPICE simulations. In order to eliminate the signal-to-noise-and-distortion ratio (SINAD) degradation caused from the poor isolation of a single-stage quantizer (1SQ), a three-stage quantizer (3SQ), which consists of three cascoded RTD quantizers, is introduced. At a sample rate of 10 Gsps (samples per a second) and a signal bandwidth of 40 MHz (oversampling ratio of 128), the modulator demonstrates a SINAD of 56 dB, which corresponds to the effective number of bits of 9.3.

A cascode crystal oscillator is widely used for the stable frequency source of mobile communication equipments. Recently, IC production of the cascode crystal oscillator has become necessary. The cascode crystal oscillator is composed of a colpitts crystal oscillator and a cascode connected base-common buffer amplifier. The base bypass condenser prevents the area size reduction. In this paper, we have proposed the new structures of the cascode crystal oscillator suitable for integrated circuits. The proposed circuits have the advantages on reduction of the area size and start-up time without deteriorating the frequency stability against the load impedance variation and other performances. The simulation and experiment have shown the effectiveness of the proposed circuits.

We have demonstrated the single-chip RF front-end GaAs MMIC for the Japanese Personal Handy-phone System. It has a high efficiency HPA, a T/R switch, a LNA and a low-distortion down converter mixer. The IC employs a negative voltage generator for use of single voltage DC power supply. The HPA provides an output power of 21.5 dBm, with an ACPR of 55 dBc and an efficiency of 35%. The LNA has a noise figure of 1.6 dB and a gain of 14 dB with current of 2.3 mA. The newly developed active cascode FET mixer has a high IIP3 of 1 dBm with a high conversion gain of 10 dB and low consumption current of 2.3 mA. The IC is characterized by high performance for RF front-end of PHS handheld terminals. The IC is available in a 7.0 mm6.4 mm1.1 mm plastic package.

An MMIC variable-gain amplifier, which improves the transmission phase deviation caused by gain control, is presented. At first, it is shown that by controlling both the common-gate FET's gate bias voltage and the common-source FET's gate bias voltage, the transmission phase deviation caused by gain control of the variable-gain amplifier using a cascode-connected FET is greatly improved. In this case it is not desirable to control both of the gate bias voltages independently, because of the complexity. Thus we propose two simple gate bias voltage control circuits controlling both of the gate bias voltages, in which only one of the two gate bias voltages is controlled independently and the other is controlled dependently. Then we apply these circuits to the 1. 9-GHz-band variable-gain amplifier using the cascode-connected FET. One of the control circuits is the gate bias voltage control circuit using two resistors. It is confirmed that, by applying the newly proposed circuit, phase deviation is suppressed, from between 0and 30to between 3and 5, with 25-dB gain control. The other circuit is the gate bias voltage control circuit using the FET's nonlinear characteristics. It is confirmed that, by applying the newly proposed circuit, phase deviation is suppressed, from between 0and 44to between 6and 3 with 30-dB gain control. This is a promising technique for reducing the transmission phase deviation caused by gain control of the amplifiers used in active phased array antennas.