The purpose of this study is to estimate the noise level of every pixel in a single noisy image, that is superimposed independent and non-identically distributed random variables with normal distribution. The method makes a set of similar pixels in the local region to the interest pixel using the approximate function of noise variance, and estimates with regard to the noise level. As the results show, the proposed method is effective in estimation of noise level of every pixel for any images.

For source camera identification, we propose a method to reconstruct the sensor pattern noise map from a size-reduced query image by minimizing an objective function derived from the observation model. Our method can be applied to multiple queries, and can thus be further improved. Experiments demonstrate the superiority of the proposed method over conventional interpolation-based magnification algorithms.

Recent attempts to directly combine CMOS pixel readout chips with modern gas detectors open the possibility to fully take advantage of gas detectors. Those conventional readout LSIs designed for hybrid semiconductor detectors show some issues when applied to gas detectors. Several new proposed readout LSIs can improve the time and the charge measurement precision. However, the widely used basic charge sensitive amplifier (CSA) has an almost fixed dynamic range. There is a trade-off between the charge measurement resolution and the detectable input charge range. This paper presents a method to apply the folding integration technique to a basic CSA. As a result, the detectable input charge dynamic range is expanded while maintaining all the key merits of a basic CSA. Although folding integration technique has already been successfully applied in CMOS image sensors, the working conditions and the signal characteristics are quite different for pixel readout LSIs for gas particle detectors. The related issues of the folding CSA for pixel readout LSIs, including the charge error due to finite gain of the preamplifier, the calibration method of charge error, and the dynamic range expanding efficiency, are addressed and analyzed. As a design example, this paper also demonstrates the application of the folding integration technique to a Qpix readout chip. This improves the charge measurement resolution and expands the detectable input dynamic range while maintaining all the key features. Calculations with SPICE simulations show that the dynamic range can be improved by 12 dB while the charge measurement resolution is improved by 10 times. The charge error during the folding operation can be corrected to less than 0.5%, which is sufficient for large input charge measurement.

The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.

This paper presents a 20 GHz push-push VCO realized by a 10 GHz super-harmonic coupled quadrature oscillator for a quadrature 60 GHz frequency synthesizer. The output nodes are peaked by a tunable second harmonic resonator. The proposed VCO is implemented in 65 nm CMOS process. It achieves a tuning range of 3.5 GHz from 16.1 GHz to 19.6 GHz with a phase noise of -106 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 10.3 mW and an FoM of -181.3 dBc/Hz is achieved.

The wideband noise controlling performance of the delayless subband adaptive filtering technique is affected by the group delay and in-band aliasing distortion of analysis filter banks. A method of recursive second-order cone programming is proposed to design the uniform DFT modulated analysis filter banks, with a small in-band aliasing error and low group delay. Simulation results show that the noise controlling performance is improved with small residual noise power spectra, a high noise attenuation level and fast convergence rate.

The effects of fluorine implantation on flicker noise and reliability of NMOSFET and PMOSFETs were concurrently investigated. The flicker noise of an NMOSFET was decreased about 66% by fluorine implantation, and that of a PMOSET was decreased about 76%. As indicated by the results, fluorine implantation is one of the methods that can be used to improve the noise characteristics of MOSFET devices. However, hot-carrier degradation was enhanced by fluorine implantation in NMOSFETs, which can be related to the difference of molecular binding within the gate oxide. On the contrary, in case of PMOSFETs, NBTI life time was increased by fluorine implantation. Therefore, concurrent investigation of hot-carrier and NBTI reliability and flicker noise is necessary in developing MOSFETs for analog/digital mixed signal applications.

The noise in digital images acquired by image sensors has complex characteristics due to the variety of noise sources. However, most noise reduction methods assume that an image has additive white Gaussian noise (AWGN) with a constant standard deviation, and thus such methods are not effective for use with image signal processors (ISPs). To efficiently reduce the noise in an ISP, we estimate a unified noise model for an image sensor that can handle shot noise, dark-current noise, and fixed-pattern noise (FPN) together, and then we adaptively reduce the image noise using an adaptive Smallest Univalue Segment Assimilating Nucleus ( SUSAN ) filter based on the unified noise model. Since our noise model is affected only by image sensor gain, the parameters for our noise model do not need to be re-configured depending on the contents of image. Therefore, the proposed noise model is suitable for use in an ISP. Our experimental results indicate that the proposed method reduces image sensor noise efficiently.

An effective supply voltage monitor evaluates dynamic variation of (Vdd-Vss) within power rails of integrated circuits on a die. The monitor occupies an area of as small as 10.8 14.5 µm2 and is followed by backend digitizing circuits, both using 3.3 V thick oxide transistors in a 65 nm CMOS technology for covering all power domains from core circuits to peripheral I/O rings. A prototype demonstrates capturing of effective supply voltage waveforms in digital (shift registers) as well as in analog (4 bit Flash ADC) circuits.

This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

During the production of speech signals, the vowel onset point is an important event containing important information for many speech processing tasks, such as consonant-vowel unit recognition and speech end-points detection. In order to realize accurate automatic detection of vowel onset points, this paper proposes a reliable method using the energy characteristics of homomorphic filtered spectral peaks. The homomorphic filtering helps to separate the slowly varying vocal tract system characteristics from the rapidly fluctuating excitation characteristics in the cepstral domain. The distinct vocal tract shape related to vowels is obtained and the peaks in the estimated vocal tract spectrum provide accurate and stable information for VOP detection. Performance of the proposed method is compared with the existing method which uses the combination of evidence from the excitation source, spectral peaks, and modulation spectrum energies. The detection rate with different time resolutions, together with the missing rate and spurious rate, are used for comprehensive evaluation of the performance on continuous speech taken from the TIMIT database. The detection accuracy of the proposed method is 74.14% for ±10 ms resolution and it increases to 96.33% for ±40 ms resolution with 3.67% missing error and 4.14% spurious error, much better than the results obtained by the combined approach at each specified time resolution, especially the higher resolutions of ±10±30 ms. In the cases of speech corrupted by white noise, pink noise and f-16 noise, the proposed method also shows significant improvement in the performance compared with the existing method.

This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

Multi-Gate device technology is the promising candidate for the enhancement of device characteristics of the scaled MOSFETs. Moreover, independent-double-gate devices have been proposed to achieve flexible Vth adjustment. It is revealed that the SRAM noise margins have been increased by introducing the independent-double-gate FinFET.

This paper describes the analysis and design of low-noise analog circuits for a new architecture readout LSI, Qpix. In contrast to conventional readout LSIs using TOT method, Qpix measures deposited charge directly as well as time information. A preamplifier with a two-stage op amp and current-copy output buffers is proposed to realize these functions. This preamplifier is configured to implement a charge sensitive amplifier (CSA) and a trans-impedance amplifier (TIA). Design issues related to CSA are analyzed, which includes gain requirement of the op amp, stability and compensation of the two-stage cascode op amp, noise performance estimation, requirement for the resolution of the ADC and time response. The offset calibration method in the TIA to improve the charge detecting sensitivity is also presented. Also, some design principles for these analog circuits are presented. In order to verify the theoretical analysis, a 400-pixel high speed readout LSI: Qpix v.1 has been designed and fabricated in 180 nm CMOS process. Calculations and SPICE simulations show that the total output noise is about 0.31 mV (rms) at the output of the CSA and the offset voltage is less than 4 mV at the output of the TIA. These are attractive performances for experimental particle detector using Qpix v.1 chip as its readout LSI.

This paper proposes a novel multichannel speech enhancement technique for reverberant rooms that is effective when noise sources are spatially stationary, such as a projector fan noise, an air-conditioner noise, and unwanted speech sources at the back of microphones. Speech enhancement performance of the conventional multichannel Wiener filter (MWF) degrades when the Signal-to-Noise Ratio (SNR) of the current microphone input signal changes from the noise-only period. Furthermore, the MWF structure is computationally inefficient, because the MWF updates the whole spatial beamformer periodically to track switching of the speakers (e.g. turn-taking). In contrast to the MWF, the proposed method reduces noise independently of the SNR. The proposed method has a novel two-stage structure, which reduces noise and distortion of the desired source signal in a cascade manner by using two different beamformers. The first beamformer focuses on noise reduction without any constraint on the desired source, which is insensitive to SNR variation. However, the output signal after the first beamformer is distorted. The second beamformer focuses on distortion reduction of the desired source signal. Theoretically, complete elimination of distortion is assured. Additionally, the proposed method has a computationally efficient structure optimized for spatially stationary noise reduction problems. The first beamformer is updated only when the speech enhancement system is initialized. Only the second beamformer is updated periodically to track switching of the active speaker. The experimental results indicate that the proposed method can reduce spatially stationary noise source signals effectively with less distortion of the desired source signal even in a reverberant conference room.

In this letter, we consider the ultimate boundedness of the singularly perturbed system with measurement noise. The composite controller is commonly used to regulate the singularly perturbed system. However, in the presence of measurement noise, the composite controller does not guarantee the ultimate boundedness of the singularly perturbed system. Thus, we propose the modified composite controller to show the ultimate boundedness of the singularly perturbed system with measurement noise.

The voltage biased SQUID Bootstrap Circuit (SBC) was recently demonstrated for direct readout of SQUID signals. The SBC combines current- and voltage-feedbacks in one circuit to suppress the preamplifier noise. It offers not only a good noise performance, but also wide tolerance of SQUID parameters. Using SBC gradiometer, the bio-magnetic signals were successfully measured. In this paper, we overview the concept of SBC and its applications.

We evaluated the single side-band phase noise of a 40 GHz beat signal generated by two free-running lasers. This allowed us to verify the utility of the two free-running lasers is verified as a light source for a next-generation radio-over-fiber system using frequency such as those in the millimeter-wave and terahertz bands. We also measured the phase noise of a frequency quadrupler using a Mach-Zehnder modulator for comparison. The phase noise of the two free-running lasers and the frequency quadrupler are -63.85 and -95.22 dBc/Hz at a 10 kHz offset frequency, respectively.

High phase noise is a common problem in ring oscillators. Continuous conduction of the transistor in an analog tuning method degrades the phase noise of ring oscillators. In this paper, a digital control tuning which completely switches the transistors on and off, and a 1/f noise reduction technique are employed to reduce the phase noise. A 14-bit control signal is employed to obtain a small frequency step and a wide tuning range. Furthermore, multiphase ring oscillator with a sub-feedback loop topology is used to obtain a stable quadrature outputs with even number of stages and to increase the output frequency. The measured DCO has a frequency tuning range from 554 MHz to 2.405 GHz. The power dissipation is 112 mW from 1.8 V power supply. The phase noise at 4 MHz offset and 2.4 GHz center frequency is -134.82 dBc/Hz. The FoM is -169.9 dBc/Hz which is a 6.3 dB improvement over the previous oscillator design.

This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm2.