The 6to4 method enables separate IPv6 sites to connect to the IPv6 Internet via a 6to4 relay router without an explicit IPv6-over-IPv4 tunnel setup. There are about a dozen open 6to4 relay routers worldwide but none of these have been installed in Japan. We therefore decided to evaluate the 6to4 mechanism and set ourselves the goal of improving the 6to4 operation within Japan. To accomplish this, in March 2002, we installed an open 6to4 relay router in Japan with the cooperation of the WIDE project and started this experiment. This paper describes our experiment and analysis of IPv6 traffic through our 6to4 relay router, as well as considerations derived from our experiment.

With the aim of applying a MISS tunnel-diode cell to a high-density RAM, we studied its problems and developed three circuit technologies to solve them. The first, a standby-voltage control scheme, reduces standby currents and increases the signal current by 3.4 times compared to the conventional one. The second, a hierarchical bit-line structure, reduces the number of memory cells in a bit-line without increasing the number of sense amplifiers. The third, a twin-dummy-cell technique, generates a proper reference signal to discriminate read currents. These technologies enable a capacitorless MISS diode cell with an effective cell area of 6F 2 (F: minimum feature size) to be applied to a high-density RAM.

The density gradient (DG) model is tested for its ability to describe tunneling currents through thin insulating barriers. Simulations of single barriers (MOS diodes, MOSFETs) and double barriers (RTDs) show the limitations of the DG model. For comparison, direct tunneling currents are calculated with the Schrodinger-Bardeen method and used as benchmark. The negative differential resistance (NDR) observed in simulating tunneling currents with the DG model turns out to be an artifact related to large density differences in the semiconductor regions. Such spurious NDR occurs both for single and double barriers and vanishes, if all semiconductor regions are equally doped.

Impact ionization and thermionic tunnelling as two possible breakdown mechanisms in scaled pseudomorphic high electron mobility transistors (PHEMTs) are investigated by Monte Carlo (MC) device simulations. Impact ionization is included in MC simulation as an additional scattering mechanism whereas thermionic tunnelling is treated in the WKB approximation during each time step in self-consistent MC simulation. Thermionic tunnelling starts at very low drain voltages but then quickly saturates. Therefore, it should not drastically affect the performance of scaled devices. Impact ionization threshold occurs at greater drain voltages which should assure a reasonable operation voltage scale for all scaled PHEMTs.

A novel multiple-valued transfer gate (T-gate) consisting of multiple-junction surface tunnel transistors (MJSTTs) and hetero-junction FETs (HJFETs) was developed and its operation was confirmed by both simulation and experiment. The number of the devices required to form the T-gate can be drastically reduced because of the high functionality of the MJSTT; namely only three MJSTTs and three HJFETs are required to fabricate the three-valued T-gate. This number of transistors is less than half that of a conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic functions. Furthermore, only one T-gate is needed to form a multiple-valued D-flip-flop (D-FF) circuit.

The IETF Mobile IP defines two multicast options: remote subscription (RS) and bi-direction tunneling (BT). In order to synthesize the strong points of these two IETF multicast options, we propose a hybrid approach, mMOM, which selectively uses two IETF multicast options based on the mobility of mobile hosts. Whenever a mobile host requests its first registration to a certain foreign agent, the corresponding foreign agent starts the service using the BT option. Afterwards, if it requests re-registration to the same foreign agent, the foreign agent considers it to be relatively immobile and continues services using the RS option. We propose a new metric to compare heterogeneous algorithms. Simulation results show that our approach outperforms all others.

The threshold voltage of Coulomb staircase using organic molecules was analyzed by extending our previous model with only consideration of the metal/organic film interfacial space charge to the generalized one. The generalized model is helpful to examine coupling capacitance in organic double barrier tunneling junction (DBTJ). The current-voltage (I-V) characteristic of metal/polyimide (PI)/rhodamine-dendrimer (Rh-G2)/PI/metal junction was analyzed using this generalized model. The calculation results were in good agreement with our experimental data.

A flash analog-to-digital converter (ADC) that uses resonant-tunneling complex gates is proposed. The ternary quantizers, consisting of monostable-to-multistable transition logic (MML) circuits, convert the analog input signal into the ternary thermometer code. This code is then converted into the binary Gray-code output by a multiple-valued multiple-input monostable-bistable transition logic element (M2-MOBILE). By assuming InP-based resonant-tunneling diode (RTD) and heterojunction field-effect transistor technology, we have carried out SPICE simulation that demonstrates a 4-bit, 10-GS/s ADC operation. The input bandwidth, defined as a frequency at which the effective number of bit decreases by 0.5 LSB, was also estimated to be 500 MHz. Compact circuit configuration, which is due to the combination of MML and M2-MOBILE, reduces the device count and power dissipation by a factor of two compared with previous RTD-based ADCs.

We report the measurements on the ramp-edge type Josephson and quasiparticle tunnel junctions with the different interface angle geometry using high-Tc YBa2Cu3O7-y (YBCO) electrodes. The YBCO/I/Ag tunnel junctions with different crystal-interface boundary angles are fabricated for the investigation of zero bias conductance peak. The angle dependent zero bias conductance peak typical to a dx2-y2-wave superconductor is observable. For Josephson junctions, YBCO ramp-edge junctions with different ab-plane electrodes relatively rotated by 45are fabricated using a CeO2 seed-layer technique. The temperature dependence of the maximum Josephson current for YBCO/PBCO/YBCO junctions (PBCO: PrBa2Cu3O7-y) exhibits angle-dependent behavior, qualitatively different from the Ambegaokar-Baratoff prediction. Under microwave irradiation of 9 GHz, the Shapiro steps appear at integer and/or half integer multiples of the voltage satisfying Josephson voltage-frequency relation, whose behavior depends on the sample angle geometry. The results are reasonably interpreted by the dx2-y2-wave theory by taking the zero energy state into account.

The low bias region of the base current has been studied in SiGe HBTs and shown to arise from tunneling at the emitter periphery. Tunneling also describes the reverse bias base-emitter current, which we believe is enhanced by mid-gap states. The reverse bias causes damage to the base-emitter region, increasing the base current. We also show that after a short period of severe reverse bias stress the base current displays random telegraph signals. These phenomena are often observed in silicon bipolar transistors, confirming that the incorporation of SiGe has not produced any other undesirable characteristics.

Magnetic tunnel junctions (MTJ), i.e., structures consisting of two ferromagnetic layers (FM1 and FM2), separated by a very thin insulator barrier (I), have recently attracted attention for their large tunneling magnetoresistance (TMR) which appears when the magnetization of the ferromagnets of FM1 and FM2 changes their relative orientation from parallel to antiparallel in an applied magnetic field. Using an ultrahigh vacuum magnetron sputtering system, a variety of MTJ structures have been explored. Double Hc magnetic tunnel junction, NiFe/Al2O3/Co and FeCo/Al2O3/Co, were fabricated directly using placement of successive contact mask. The tunnel barrier was prepared by in situ plasma oxidation of thin Al layers sputter deposited. For NiFe/Al2O3/Co junctions, the maximum TMR value reaches 5.0% at room temperature, the switching field can be less than 10 Oe and the relative step width is about 30 Oe. The junction resistance changes from hundreds of ohms to hundreds of kilo-ohms and TMR values decrease monotonously with the increase of applied junction voltage bias. For FeCo/Al2O3/Co junctions, TMR values exceeding 7% were obtained at room temperature. It is surprising that an inverse TMR of 4% was observed in FeCo/Al2O3/Co. The physics governing the spin polarization of tunneling electrons remains unclear. Structures, NiFe/FeMn/NiFe/Al2O3/NiFe, in which one of the FM layers is exchange biased with an antiferromagnetic FeMn layer, were also prepared by patterning using optical lithography techniques. Thus, the junctions exhibit two well-defined magnetic states in which the FM layers are either parallel or antiparallel to one another. TMR values of 16% at room temperature were obtained. The switching field is less than 10 Oe and step width is larger than 30 Oe.

Current-voltage characteristics of Cr-doped hydrogenated amorphous silicon-V (Cr/p+a-Si:H/V) analogue memory switching devices have been measured over a wide range of device resistance from several kilo-ohms to several hundred kilo-ohms, and over a temperature range from 13 K to 300 K. Both the bias and temperature dependence of the conductance show similar characteristics to that of metal-insulator heterogeneous materials (i.e. discontinuous or granular metallic films), which are analysed in terms of activated tunnelling mechanism. A modified filamentary structure for the Cr/p+a-Si:H/V switching devices is proposed. The influence of embedded metallic particles on memory switching is analysed and discussed.

The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.

Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p+-n+ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.

The unidirectional transmission links such as broadcast satellite links and cable links are strongly demanding type of link to provide high bandwidth and ubiquitous Internet connectivity with lower cost. In order to provide an internet connectivity, the UDLs, unidirectional links, should be available for the IP service. However, since the current Internet routing and upper layer protocols assume the bi-directional link, the UDLs have been considered as unavailable links for the IP service. This paper proposes an architecture and a mechanism for the IP service over the UDL. The proposed system emulates the bi-directional connectivity between all nodes on the UDL, in order to use the dynamic routing protocol, the TCP/IP protocol, on the UDL system. Receiver uses a link layer tunneling mechanism to forward the IP datagrams to the Feed over an IP cloud, that is not directly connected to the UDL. This proposed architecture enables the dynamic routing capability for UDLs, as well as user applications, without any software modification.

This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.

Magnetic random access memory (MRAM) possesses the attractive properties of non-volatility, radiation hardness, nondestructive readout, low voltage, high access speed, unlimited read and write endurance and high density. MRAM technology is described for the devices using giant magnetoresistance (GMR) and tunneling magnetoresistance (TMR) materials in this paper. The TMR type MRAM architectures using ferromagnetic tunneling junctions (MTJ) are more attractive for mainstream RAM applications than the GMR type, because the signal of the TMR type is larger than that of the GMR type. A MRAM device with an MTJ plus MOS transistor switch architecture, which can provide large signal-to noise ratio, is detailed. A design of the MTJ element is discussed and the requirements for the junction resistance and the TMR needed for the memory device are demonstrated based on the simple signal voltage calculations. The TMR significantly decreases with increasing bias voltage, which leads to the reduction of the signal voltage for the actual MRAM. A ferromagnetic double tunneling junction is proposed for the high density MRAM application demanding large signal voltage, because of the smaller degradation of the TMR for the bias voltage, compared with that of the conventional single junctions. Recent trials of MRAM fabrication are introduced, which demonstrates high-speed access time. Finally, challenges for the higher bit density MRAM above Gb are discussed, and it is noticed that higher signal voltage, lower power consumption for writing and novel cell designs are needed for the achievement.

We have manufactured large-scaled highly reliable MNOS EEPROMs over the last twenty years. In particular, at the present time, the smart-card microcontroller incorporating an embedded 32-kB MNOS EEPROM is rapidly expanding the markets for mobile applications. It might be said that we have established the conventional MNOS nonvolatile semiconductor memory technology. This paper describes the device design concepts of the MNOS memory, which include the optimization and control of the tunnel oxide film thickness (1.8 nm), and the scaling guideline that considers the charge distribution in the trapping nitride film. We have developed a high-performance MONOS structure and have not found any failure due to the MONOS devices in high-density EEPROM products during 10-year data retention tests after 105 erase/write cycles. The future development of this highly reliable MNOS-type memory will be focussed on the high-density cell structure and high-speed programming method. Recently, some promising ideas for utilizing an MNOS-type memory device, such as 1-Tr/bit cell for byte-erasable full-featured EEPROMs and 2-bit/Tr cell for flash EEPROMs have been proposed. We are convinced that MNOS technology will advance into the area of nonvolatile semiconductor memories because of its high reliability and high yield of products.

Present status of the development of superconducting tunnel junctions for the detection of X-ray photons and heavy ions is reported. The energy resolution for 5.9 keV X-rays was measured to be 41 eV, 58 eV, 65 eV and 129 eV with STJs of 2020 µm2, 100100 µm2, 200200 µm2 and 500500 µm2, respectively, and a model to describe the phonon-mediated X-ray signals is discussed. Direct voltage switching induced by heavy ions was successfully observed.

The capability of frequency-swept cross-borehole radar to detect an empty rectangular cylinder embedded in a dielectric medium is simulated numerically by employing the boundary element method. The frequency loci providing the strongest double dips in the received signal pattern are plotted as functions of the observation distance and the cross-sectional width. It is found that, regardless of the shape of the rectangular cross-section, the strongest double dips become double nulls in the near-field region.