A Superconductor-Insulator-Superconductor (SIS) mixer using two junctions connected in parallel through a stripline inductance has been studied. The essential point of the two-junctions device is that the capacitance of the junctions was tuned out by the inductance to obtain a broadband operation without mechanical tuning elements. It has been shown by theoretical analysis that the performance of this type of device is excellent and nearly quantum-limited performance of the mixer can be obtained. It has been demonstrated that the double sideband (DSB) noise temperature of a receiver employing this type of device was less than 40 K over the bandwidth of 90-120 GHz and that the lowest receiver noise temperature of 18 K, which is only 3.2 times as large as the quantum limited photon noise was obtained around 118 GHz. Junctions used in the two-junctions device have significantly larger area, i.e. larger capacitance, and smaller normal resistance than conventional ones. In order to obtain a good impedance match between the source and the junctions, an impedance transformer made of a superconductiong stripline was integrated with the junctions. This type of two-junctions device can easily be scaled to submillimeter frequency without using submicron-sized SIS junctions.

The transistor action with negative differential resistance (NDR) of a nanometer-thick metal (CoSi2)/insulator (CaF2) resonant tunneling transistor is discussed for two transistor structures. These transistors are composed of metal-insulator (M-I) heterostructures with two metallic (CoSi2) quantum wells and three insulator (CaF2) barriers grown on an n-Si (lll) substrate. One of the two structures has the base terminal connected to one of the quantum wells next to the collector, and the other, to one next to the emitter. Although base resistance is high maybe due to the damage caused during the fabrication process, the two transistors show different characteristics, as expected theoretically. Transfer efficiency α (= IC/IE) close to unity was obtained at 77 K for electrons through the resonant levels in M-I heterostructures.

Gate-controlled negative differential resistance (NDR) due to interband tunneling has been observed at room temperature in a Surface Tunnel Transistor (STT). The STT consists of a highly degenerate p+-drain, an n+-doped channel with an insulated gate, and an n+-source connected to the channel. To demonstrate application as a functional device, a bistable circuit consisting of only one STT and one load resistor was organized and its operation was confirmed. The obtained valley current in the NDR characteristics of the STT, however, is relatively large and limits the device performance. In order to clarify the origin of the valley current, we fabricated p+-n+ tunnel diodes in which growth interruption was done at the pn junction, and investigated the dependence of the NDR characteristics on both the impurity concentration at the regrown interface and the temperature. These measurements indicate that the valley current is mainly caused by the excess tunneling current through traps formed by the residual oxygen at the regrown interface.

Fabrication of all-epitaxial high-Tc SIS tunnel junctions requires an atomically flat superconducting thin film to be grown and a proper insulating material to be selected. First, we study the initial growth mode of YBCO thin films and show that reducing the growth rate results in a very smooth surface. Second, perovskite-related compound oxides, PrGaO3 and NdGaO3, which have a small lattice mismatch with YBCO and good wetability, are shown to be promising insulating materials for all-epitaxial SIS tunnel junctions. We believe that these concepts will be useful in the development of all-epitaxial high-Tc SIS tunnel junctions with good electrical properties.

We have fabricated Nb/AlOx/Nb Josephson tunnel junctions by a sputtering apparatus with a load-lock system. This sputtering apparatus had the sub chamber for preparation and the main chamber for sputtering. The substrate temperature was confirmed to be kept less than 85 during Nb sputtering at the deposition rate of 1.18 nm/s for 7 minutes. The junctions that had 50µm50 µm area successfully showed the Vm value (the product of the critical current and the subgap resistance at 2 mV) as high as 50 mV at the current density of 100 A/cm2.

A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm2 cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm2 cell size for a 0.5 µm 64 Mbit flash memory, is described.

We compare interfaces of Nb/AlOx-Al/Nb and Nb/ZrOx-Zr/Nb junctions using secondary ion mass spectroscopy and cross-sectional transmission electron microscopy. We have clarified that an interface of the Nb/AlOx-Al/Nb junction is drastically different from that of the Nb/ZrOxZr/Nb junction. An adsorbed water vapor layer plays an important role in suppressing grain boundary diffusion between Nb and Al at the interface of the Nb/AlOxAl/Nb junction. In depositing Nb and Al at low power and cooling the substrate, it is important to control the formation of the adsorbed water vapor layer for fabricating Nb/AlOx-Al/Nb junctions exhibiting excellent current-voltage characteristics.

A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are8 V and 12 V, respectively. The use of low positive internal-voltages results in reducing total process step numbers compared with reported memory cells. The HiCR cell also realizes low power and fast random access with a single 3 V power-supply.

The data retention characteristics of a Flash memory cell with a self-aligned double poly-Si stacked structure have been drastically improved by applying a bi-polarity write and erase technology which uses uniform Fowler-Nordheim tunneling over the whole channel area both during write and erase. It is clarified experimentally that the detrapping of electrons from the gate oxide to the substrate results in an extended retention time. A bi-polarity write and erase technology also guarantees a wide cell threshold voltage window even after 106 write/erase cycles. This technology results in a highly reliable EEPROM with an extended data retention time.

We fabricated junctions with a porphyrin polyimide (PORPI) monolayer, and then investigated the electron transport properties of the junctions from the current-voltage (I-V) and d2V/dI2-V measurements. Polyimide LB films without porphyrin were used as tunneling barriers. One large peak was seen at a voltage around 1.9 V, due to the excitation of electron transitions in PORPI molecules, whereas a step structure was not observed in the I-V characteristic.

To investigate the effect of alkyl chain length and adsorption time on the charge-transfer complex formation, ultraviolet-visible absorption and inelastic electron tunneling (IET) spectroscopy measurements were carried out for the tetramethylphenylenediamine (TMPD; donor molecule) adsorbed dodecyl-, pentadecyl- and octadecyl-tetracyanoquinodimethane (TCNQ) Langmuir-Blodgett (LB) films. In the optical absorption spectra, the main peak of LB films shows a red-shift depending on alkyl chain length and adsorption time. Furthermore, the dependence on alkyl chain length and adsorption time are also shown in the IET spectra. These results demonstrate that adsorption LB methods enable to control the adsorption ratio of functional molecules and the CT complex formation.

Electrical and optical properties of organic multilayer structure have been investigated. Two types of current-voltage characteristics have been found for thin multilayer structure of organic films. Optical property and its application for electroluminescent diode have been presented. The diode characteristics have been discussed in terms of energy band scheme.

A Si metal insulator semiconductor tunnel emitter transistor (Si MIS TET) which is a new type of bipolar transistor was fabricated and its electrical properties for the temperature range of 100 K - 300 K were investigated. The common emitter mode current gain obtained was 75 at 300 K and 74 at 100 K. It was confirmed by measuring the temperature dependence of the base current that the inversion base layer indeed functioned as a base of the Si MIS TET. The current gain of the Si MIS TET did not decrease at low temperature of 100 K, though the current gain of the conventional Si bipolar transistor decreases at low temperature due to the emitter bandgap narrowing in heavily doped emitter. This origin was that the carrier injection mechanism between the emitter and the base was tunneling.

Leakage enhancement after an ESD event has been analyzed for output buffer LDD MOSFETs. The HBM ESD failure threshold for the LDD MOSFETs is only 200-300 V and the failure is the leakage enhancement of the off-state MOSFETs called as "soft breakdown" leakage. This leakage enhancement is supposed to be caused by trapped electrons in the gate oxide and/or creation of interface states at the gate overlapped drain region due to snap-back stress during the ESD event. The mechanism of the lekage can be explained by band-to-band and/or interface state-to-band tunneling of electrons. The improvement of the HBM ESD threshold has been also evaluated by using two types of drain engineering which are additional arsenic implantation for the output LDD MOSFETs and "offset" gate MOSFET as a protection circuit for the output pins. By using these drain engineering, the threshold can be improved to more than 2000 V.

The Cooper pairing interaction in high Tc oxide superconductor is discussed in terms of an empirical expression; TcDexp[1/g], gcωo which was derived in our previous investigation. The dual character of this expression consisting of the phonon Debye temperature D and electronic excitation ωo in the mid-infrared region can be interpreted on the basis of the phonon-assisted mechanism on carrier conduction and the electronic excitation. A tunneling spectrum here presented shows certain evidence of the phonon contribution. The characteristics of the long range superconductive proximity phenomena recently reported are also may be interpreted by this mechanism.

In order to investigate the characteristics of the superconducting gap structures of BSCCO oxide superconductor, tunneling spectrum measurements were carried out with several junctions on the bulk single crystal surfaces. Point contact tunneling studies by means of the M/I/S and S/(I)/S junctions have shown the reproducible gap values, 2Δ (//c-axis) of 402 meV, at the cleaved crystal surfaces, and the ratio of 2Δ(//)/kBTc5.50.3 indicates the strong coupling superconductor of this material. Somewhat larger gap values, 2Δmax(c-axis)701 meV, have been also observed at the lateral surface, and these various gap values observed on each surface of the same crystal indicate the characteristic of the large gap anisotropy, Δ()/Δ(//)1.8, of this material.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

A 1/2 frequency divider using resonant-tunneling hot electron transistors (RHETs) has been proposed and demonstrated. The circuit make the best use of negative differential conductance, a feature of RHETs, and contains one half transistors than used in conventional circuits. The RHETs were fabricated using self-aligned InGaAs RHETs and WSiN thin-film resistors on a single chip. The RHETs have an i-InGaAlAs/i-InGaAs collector barrier that improves the current gain at low collector-base voltages. Circuit operation was confirmed at 77 K.

In two-dimensional simulation of thin-base RHET, we combined three different simulation methods--the Schrödinger equation, the Monte Carlo simulation, and two-dimensional device simulation within a drift and diffusion model. We found that, in the thin-base RHET, the potential distribution differs from that expected from the thick-base RHET. In the thin-base RHET, the potential of the intrinsic base region does not equal that of the base electrode because the intrinsic base region is depleted and the negative emitter voltage (VEB0) raises the potential of both the intrinsic base and the nondoped region under the intrinsic base. There are also modified by the collector voltage. We also show emitter current-voltage characteristics, transfer ratio, and transit time calculated using this method and compare them with results for the one-dimensional case.